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VCBUP8168CCYG2 Datasheet(PDF) 1 Page - Texas Instruments |
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VCBUP8168CCYG2 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 328 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320DM8168, TMS320DM8167 TMS320DM8165 SPRS614F – MARCH 2011 – REVISED MARCH 2015 TMS320DM816x DaVinci™ Digital Media Processors 1 Device Overview 1.1 Features 1 • High-Performance DaVinci Digital Media • System Memory Management Unit (System MMU) Processors – Maps C674x DSP and EMDA TCB Memory – ARM® Cortex™-A8 RISC Processor Accesses to System Addresses • 512KB of On-Chip Memory Controller (OCMC) • Up to 1.20 GHz RAM – C674x™ VLIW DSP • Media Controller • Up to 1 GHz – Manages HDVPSS and HDVICP2 Modules • Up to 8000 MIPS and 6000 MFLOPS • Up to Three Programmable High-Definition Video • Fully Software-Compatible with C67x+ and Image Coprocessing (HDVICP2) Engines C64x+™ – Encode, Decode, Transcode Operations • ARM Cortex-A8 Core – H.264, MPEG-2, VC-1, MPEG-4 SP and ASP – ARMv7 Architecture • SGX530 3D Graphics Engine (Available Only on • In-Order, Dual-Issue, Superscalar Processor the DM8168 Device) Core – Delivers up to 30 MTriangles per Second • NEON™ Multimedia Architecture – Universal Scalable Shader Engine – Supports Integer and Floating Point (VFPv3- – Direct3D® Mobile, OpenGL® ES 1.1 and 2.0, IEEE754 Compliant) OpenVG™ 1.1, OpenMax™ API Support • Jazelle® RCT Execution Environment – Advanced Geometry DMA Driven Operation • ARM Cortex-A8 Memory Architecture – Programmable HQ Image Anti-Aliasing – 32-KB Instruction and Data Caches • Endianness – 256-KB L2 Cache – ARM, DSP Instructions and Data – Little Endian – 64-KB RAM, 48-KB of Boot ROM • HD Video Processing Subsystem (HDVPSS) • TMS320C674x Floating-Point VLIW DSP – Two 165-MHz HD Video Capture Channels – 64 General-Purpose Registers (32-Bit) • One 16-Bit or 24-Bit and One 16-Bit Channel – Six ALU (32-Bit and 40-Bit) Functional Units • Each Channel Splittable Into Dual 8-Bit • Supports 32-Bit Integer, SP (IEEE Single Capture Channels Precision, 32-Bit) and DP (IEEE Double – Two 165-MHz HD Video Display Channels Precision, 64-Bit) Floating Point • One 16-Bit, 24-Bit, 30-Bit Channel and One • Supports up to Four SP Adds Per Clock and 16-Bit Channel Four DP Adds Every Two Clocks – Simultaneous SD and HD Analog Output • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root – Digital HDMI 1.3 Transmitter with PHY with Operations Per Cycle HDCP up to 165-MHz Pixel Clock – Two Multiply Functional Units – Three Graphics Layers • Mixed-Precision IEEE Floating-Point Multiply • Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces Supported up to: – Supports up to DDR2-800 and DDR3-1600 – 2 SP x SP → SP Per Clock – Up to Eight x8 Devices Total – 2 SP x SP → DP Every Two Clocks – 2GB of Total Address Space – 2 SP x DP → DP Every Three Clocks – Dynamic Memory Manager (DMM) – 2 DP x DP → DP Every Four Clocks • Programmable Multi-Zone Memory Mapping • Fixed-Point Multiply Supports Two 32 x 32 and Interleaving Multiplies, Four 16 x 16-Bit Multiplies • Enables Efficient 2D Block Accesses Including Complex Multiplies, or Eight 8 x 8- • Supports Tiled Objects in 0°, 90°, 180°, or Bit Multiplies per Clock Cycle 270° Orientation and Mirroring • C674x Two-Level Memory Architecture • Optimizes Interlaced Accesses – 32-KB L1P and L1D RAM and Cache • One PCI Express® (PCIe) 2.0 Port with Integrated – 256-KB L2 Unified Mapped RAM and Caches PHY 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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