DDR2 datasheets specify VDD, VDDQ, and VDDL condition as 1.8V+-100mV. This specification is a DC

condition for the device that assumes ideal voltage conditions without current deficiencies. VDD and

VDDQ often share the same power plane in the board, which can result in level shifts on VDD. This

condition is caused by DDR2 high frequency I/O switching (VDDQ) which consumes a large amount of

current vs VDD requirements. In typical DDR2 applications, most voltage variations are caused by

current limitations, which are the result dynamic power requirements that change over the course of

the various operational modes of the DRAM.

The following charts illustrate current deficiencies and voltage drop(s) caused by a change in the

operating mode from standby to active. Major factors that contribute to current deficiencies in DDR2

applications are inductances and power supply design methodologies.

Inductances are resistive to current changes, acting as a constraint to the amount of instantaneous

current that is available when operating modes change. When the device transitions from standby to

active mode, the current demand increases rapidly (Fig 1 - Green trace). If a board design has

excessive supply path inductances, this sudden demand increase can easily exceed the capability of

the power supply to provide the needed current. The current deficiency resulting from the high

inductance is highlighted by the red triangle. The lack of current is visible in the voltage drop (Fig 1 -

Yellow trace) until the power supply can provide enough current to meet the active power

requirements. Because of this potential phenomenon, supply path inductances should be minimized

and voltage drops should not exceed 50mV (duration must be < 20us), nor should they exceed 70mV

(duration must be < 10us).

[Fig 1.] Voltage dip caused by inductive supply paths resulting in VDD/VDDQ current deficiencies.

Power supply responds immediately after device consume

the current

220mA

60mA

Operating Period

Standby Period