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IS25WQ040 Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc |
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IS25WQ040 Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc |
8 / 65 page IS25WQ040/020 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/05/2014 8 4. SPI MODES DESCRIPTION Multiple IS25WQ040/020 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 4.1 the devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure 4.2 for SPI mode. In SPI mode, the input data is latched on the rising edge of Serial Clock (SCK), and the output data is available from the falling edge of SCK. Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices) Notes: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as necessary. 2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively during Multi-IO mode. SPI interface with (0,0) or (1,1) SPI Master (i.e. Microcontroller) SPI Memory Device SPI Memory Device SPI Memory Device SCK SO SI SCK SDI SDO CE# WP# HOLD# SCK SO SI CE# WP# HOLD# SCK SO SI CE# WP# HOLD# CS3 CS2 CS1 PRELIMINARY INFORMATION |
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