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IS25WD040-JKLA Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS25WD040-JKLA Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
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10 / 35 page  IS25WD020/040 Integrated Silicon Solution, Inc.- www.issi.com Rev. F 07/31/2013 10 DEVICE OPERATION The IS25WD020/040 utilize an 8-bit instruction register. Refer to Table 10 Instruction Set for details of the Instructions and Instruction Codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on Serial Data Input (SI). The input data on SI is latched on the rising edge of Serial Clock (SCK) after Chip Enable (CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. CE# must be driven high (VIH) after the last bit of the instruction sequence has been shifted in. The timing for each instruction is illustrated in the following operational descriptions. Table 10. Instruction Set Instruction Name Hex Code Operation Command Cycle Maximum Frequency RDID Abh Read Manufacturer and Product ID 4 Bytes 80 MHz JEDEC ID READ 9Fh Read Manufacturer and Product ID by JEDEC ID Command 1 Byte 80 MHz RDMDID 90h Read Manufacturer and Device ID 4 Bytes 80 MHz WREN 06h Write Enable 1 Byte 80 MHz WRDI 04h Write Disable 1 Byte 80 MHz RDSR 05h Read Status Register 1 Byte 80 MHz WRSR 01h Write Status Register 2 Bytes 80 MHz READ 03h Read Data Bytes from Memory at Normal Read Mode 4 Bytes 30 MHz FAST_READ 0Bh Read Data Bytes from Memory at Fast Read Mode 5 Bytes 80 MHz FRDO 3Bh Fast Read Dual Output 5 Bytes 80 MHz PAGE_ PROG 02h Page Program Data Bytes Into Memory 4 Bytes + 256B 80 MHz SECTOR_ER D7h/ 20h Sector Erase 4 Bytes 80 MHz BLOCK_ER D8h Block Erase 4 Bytes 80 MHz CHIP_ER C7h/ 60h Chip Erase 1 Byte 80 MHz HOLD OPERATION HOLD# is used in conjunction with CE# to select the IS25WD020/040. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to Sl will be ignored while SO is in the high impedance state. |
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