IS25LQ512B datasheet(6/66 Pages) ISSI

Part #	IS25LQ512B

Description	3V QUAD SERIAL FLASH MEMORY WITH MULTI-I/O SPI

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

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6 / 66 page

IS25LQ025/512/010/020/040B

Integrated Silicon Solution, Inc.- www.issi.com

Rev.A

12/12/2014

6

2. PIN DESCRIPTIONS

SYMBOL

TYPE

DESCRIPTION

CE#

INPUT

Chip Enable: The Chip Enable (CE#) pin enables and disables the devices operation.

When CE# is high the device is deselected and output pins are in a high impedance

state. When deselected the devices non-critical internal circuitry power down to allow

minimal levels of power consumption while in a standby state.

When CE# is pulled low the device will be selected and brought out of standby mode.

The device is considered active and instructions can be written to, data read, and

written to the device. After power-up, CE# must transition from high to low before a

new instruction will be accepted.

Keeping CE# in a high state deselects the device and switches it into its low power

state. Data will not be accepted when CE# is high.

SI (IO0),

SO (IO1)

INPUT/OUTPUT

Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):

This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI

instructions use the unidirectional SI (Serial Input) pin to write instructions, addresses,

or data to the device on the rising edge of the Serial Clock (SCK). Standard SPI also

uses the unidirectional SO (Serial Output) to read data or status from the device on

the falling edge of the serial clock (SCK).

In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write

instructions, addresses or data to the device on the rising edge of the Serial Clock

(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI

instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.

WP# (IO2)

INPUT/OUTPUT

Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from

being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the

WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are

write-protected and vice-

versa for WP# high. When the SRWD is set to “0”, the Status

Register is not write-protected regardless of WP# state.

When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available

since this pin is used for IO2.

HOLD# (IO3)

INPUT/OUTPUT

Hold/Serial Data IO (IO3): Pauses serial communication by the master device

without resetting the serial sequence. When the QE bit of Status Register is set to

“1”, HOLD# pin is not available since it becomes IO3.

The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin is

active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at high

impedance.

Device operation can resume when HOLD# pin is brought to a high state. When the

QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available

and becomes IO3 for Multi-I/O SPI mode.

SCK

INPUT

Serial Data Clock: Synchronized Clock for input and output timing operations.

Vcc

POWER

Power: Device Core Power Supply

GND

GROUND

Ground: Connect to ground when referenced to Vcc

NC

Unused

NC:

Pins labeled “NC” stand for “No Connect” and should be left uncommitted.

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