Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. C

12/21/09

IS41LV44052B

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• FastPageModeAccessCycle

• TTLcompatibleinputsandoutputs

• RefreshInterval:

-- 2,048 cycles/32 ms

• RefreshMode:RAS-Only,

CAS

-before-RAS(CBR),andHidden

• Singlepowersupply:

3.3V ± 10%

• ByteWriteandByteReadoperationviatwoCAS

• Industrialtemperaturerange-40°Cto85°C

DESCRIPTION

The

CMOSDynamicRandomAccessMemory.TheFastPage

Mode allows 2,048 or 4096 random accesses within a

single row with access cycle time as short as 20 ns per

4-bit word.

These features make the IS41LV44052B ideally suited

for high-bandwidth graphics, digital signal processing,

high-performance computing systems, and peripheral

applications.

TheIS41LV44052Bispackagedina24-pinTSOP-IIwith

JEDECstandardpinouts.

4M x 4 (16-MBIT) DYNAMIC RAM

WITH FAST PAGE MODE

JANUARY 2010

KEY TIMING PARAMETERS

Parameter

-50

-60

Unit

RAS

50

60

ns

CAS

13

15

ns

25

30

ns

20

25

ns

84

104

ns

PRODUCT SERIES OVERVIEW

Part No.

Refresh

Voltage

IS41LV44052B

2K

3.3V±10%

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

VCC

I/O0

I/O1

WE

RAS

*A11(NC)

A10

A0

A1

A2

A3

VCC

GND

I/O3

I/O2

CAS

OE

A9

A8

A7

A6

A5

A4

GND

*A11isNCfor2KRefreshdevices.

PIN DESCRIPTIONS

A0-A10

AddressInputs(2KRefresh)

I/O0-3

DataInputs/Outputs

WE

WriteEnable

OE

Output Enable

RAS

RowAddressStrobe

CAS

Column Address Strobe

Vcc

Power

GND

Ground

NC

No Connection

PIN CONFIGURATION

24 (26) Pin TSOP-II