Integrated Silicon Solution, Inc.

3

Rev.  A

11/09/2010

IS42SM32160C

IS42RM32160C

Symbol

Type

Description

CLK

Input

Clock:CLKisdrivenbythesystemclock.AllSDRAMinputsignalsaresampledonthepositiveedgeof

CLK.CLKalsoincrementstheinternalburstcounterandcontrolstheoutputregisters.

CKE

Input

ClockEnable:CKEactivates(HIGH)anddeactivates(LOW)theCLKsignal.IfCKEgoeslowsynchronously

withclock(set-upandholdtimesameasotherinputs),theinternalclockissuspendedfromthenextclock

cycleandthestateofoutputandburstaddressisfrozenaslongastheCKEremainslow.Whenallbanks

areintheidlestate,deactivatingtheclockcontrolstheentrytothePowerDownandSelfRefreshmodes.

CKEissynchronousexceptafterthedeviceentersPowerDownandSelfRefreshmodes,whereCKE

becomesasynchronousuntilexitingthesamemode.Theinputbuffers,includingCLK,aredisabledduring

PowerDownandSelfRefreshmodes,providinglowstandbypower.

BA0, BA1

Input

Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge

commandisbeingapplied.

A0-A12

Input

AddressInputs:A0-A12aresampledduringtheBankActivatecommand(rowaddressA0-A12)andRead/

Writecommand(columnaddressA0-A8withA10definingAutoPrecharge)toselectonelocationinthe

respectivebank.DuringaPrechargecommand,A10issampledtodetermineifallbanksaretobeprecharged

(A10=HIGH).

Theaddressinputsalsoprovidetheop-codeduringaModeRegisterSet.

CS

Input

ChipSelect:CSenables(sampledLOW)anddisables(sampledHIGH)thecommanddecoder.Allcommands

aremaskedwhenCSissampledHIGH.CSprovidesforexternalbankselectiononsystemswithmultiple

banks.Itisconsideredpartofthecommandcode.

RAS

Input

RowAddressStrobe:TheRASsignaldefinestheoperationcommandsinconjunctionwiththeCASand

WE

signalsandislatchedatthepositiveedgesofCLK.WhenRASandCSareasserted“LOW”andCAS

isasserted“HIGH,”eithertheBankActivatecommandorthePrechargecommandisselectedbytheWE

signal.WhentheWEisasserted“HIGH,”theBankActivatecommandisselectedandthebankdesignated

byBAisturnedontotheactivestate.WhentheWEisasserted“LOW,”thePrechargecommandisselected

andthebankdesignatedbyBAisswitchedtotheidlestateaftertheprechargeoperation.

CAS

Input

ColumnAddressStrobe:TheCASsignaldefinestheoperationcommandsinconjunctionwiththeRAS

andWEsignalsandislatchedatthepositiveedgesofCLK.WhenRASisheld“HIGH”andCSisasserted

“LOW,”thecolumnaccessisstartedbyassertingCAS”LOW.”Then,theReadorWritecommandisselected

byassertingWE“LOW”or“HIGH.”

WE

Input

WriteEnable:TheWEsignaldefinestheoperationcommandsinconjunctionwiththeRASandCASsignals

andislatchedatthepositiveedgesofCLK.TheWEinputisusedtoselecttheBankActivateorPrecharge

commandandReadorWritecommand.

DQM0-3

Input

DataInput/OutputMask:DQM0-DQM3arebytespecific,nonpersistentI/Obuffercontrols.TheI/Obuffers

areplacedinahigh-zstatewhenDQMissampledHIGH.InputdataismaskedwhenDQMissampled

HIGHduringawritecycle.Outputdataismasked(two-clocklatency)whenDQMissampledHIGHduring

areadcycle.DQM3masksDQ31-DQ24,DQM2masksDQ23-DQ16,DQM1masksDQ15-DQ8,andDQM0

masksDQ7-DQ0

DQ0-31

Input/ 

Output

DataI/O:TheDQ0-31inputandoutputdataaresynchronizedwiththepositiveedgeofCLK.TheI/Osare

byte-maskableduringReadsandWrites.

PIN DESCRIPTIONS