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IS42VS16100F Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS42VS16100F Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
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1 / 86 page  Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A 06/13/2012 Copyright©2012IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithout notice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersareadvisedtoobtainthe latestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts. IS42/45S16100F, IS42VS16100F IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreason- ablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenotauthorizedforuseinsuchapplications unlessIntegratedSiliconSolution,Inc.receiveswrittenassurancetoitssatisfaction,that: a.)theriskofinjuryordamagehasbeenminimized; b.)theuserassumeallsuchrisks;and c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances JUNE 2012 FEATURES • Clockfrequency: IS42/45S16100F:200,166,143MHz IS42VS16100F:133,100MHz • Fullysynchronous;allsignalsreferencedtoa positiveclockedge • Twobankscanbeoperatedsimultaneouslyand independently • DualinternalbankcontrolledbyA11 (bankselect) • Singlepowersupply: IS42/45S16100F:Vdd/Vddq=3.3V IS42VS16100F:Vdd/Vddq=1.8V • LVTTLinterface • Programmableburstlength –(1,2,4,8,fullpage) • Programmableburstsequence: Sequential/Interleave • 2048refreshcyclesevery32ms • Randomcolumnaddresseveryclockcycle • ProgrammableCASlatency(2,3clocks) • Burstread/writeandburstread/singlewrite operationscapability • Burstterminationbyburststopand prechargecommand • BytecontrolledbyLDQMandUDQM • Packages400-mil50-pinTSOP-IIand60-ball BGA • Lead-freepackageoption • AvailableinIndustrialTemperature DESCRIPTION ISSI’s16MbSynchronousDRAMIS42S16100F, IS45S16100FandIS42VS16100Fareeachorganized asa524,288-wordx16-bitx2-bankforimproved performance.ThesynchronousDRAMsachievehigh- speeddatatransferusingpipelinearchitecture.All inputsandoutputssignalsrefertotherisingedgeofthe clockinput. 512K Words x 16 Bits x 2 Banks 16Mb SDRAM Parameter IS42/45S16100F IS42VS16100F PowerSupplyVdd/Vddq 3.3V 1.8V RefreshCount 2K/32ms 2K/32ms RowAddressing A0-A10 ColumnAddressing A0-A7 BankAddressing A11 PrechargeAddressing A10 ADDRESS TABLE Parameter -5(1) -6(2) -7 (2) -75 (3) -10 (3) Unit CLK Cycle Time CAS Latency = 3 5 6 7 7.5 10 ns CAS Latency = 2 10 10 10 10 12 ns CLK Frequency CAS Latency = 3 200 166 143 133 100 Mhz CAS Latency = 2 100 100 100 100 83 Mhz Access Time from Clock CAS Latency = 3 5 5.5 5.5 6 7 ns CAS Latency = 2 6 6 6 8 8 ns KEY TIMING PARAMETERS Notes: 1. Available for IS42S16100F only 2. Available for IS42S16100F and IS45S16100F only 3. Available for IS42VS16100F only |
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