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IS42VS16100E-75BLI Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc

Part # IS42VS16100E-75BLI
Description  2048 refresh cycles every 32 ms
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS42VS16100E-75BLI Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc

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IS42VS16100E
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev.00E
01/21/2011
Copyright©2011IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithout
notice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersareadvisedtoobtainthelat-
estversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.
IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreason-
ablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenotauthorizedforuseinsuchapplications
unlessIntegratedSiliconSolution,Inc.receiveswrittenassurancetoitssatisfaction,that:
a.)theriskofinjuryordamagehasbeenminimized;
b.)theuserassumeallsuchrisks;and
c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances
PRELIMINARYINFORMATION
FEBRUARY2011
FEATURES
• Clockfrequency:133,100,83MHz
• Fullysynchronous;allsignalsreferencedtoa
positiveclockedge
• Twobankscanbeoperatedsimultaneouslyand
independently
• DualinternalbankcontrolledbyA11
(bankselect)
• Single1.8Vpowersupply
• LVTTLinterface
• Programmableburstlength
–(1,2,4,8,fullpage)
• Programmableburstsequence:
Sequential/Interleave
• 2048refreshcyclesevery32ms
• Randomcolumnaddresseveryclockcycle
• ProgrammableCASlatency(2,3clocks)
• Burstread/writeandburstread/singlewrite
operationscapability
• Burstterminationbyburststopand
prechargecommand
• BytecontrolledbyLDQMandUDQM
• Package400-mil50-pinTSOPIIand60-ball
BGA
• Lead-freepackageoption
• Autorefreshandself-refreshmodes
• Powerdownanddeeppowerdown
DESCRIPTION
ISSI’s16MbSynchronousDRAMIS42VS16100Eis
organizedasa524,288-wordx16-bitx2-bankfor
improvedperformance.ThesynchronousDRAMs
achievehigh-speeddatatransferusingpipeline
architecture.Allinputsandoutputssignalsrefertothe
risingedgeoftheclockinput.
512KWordsx16Bitsx2Banks
16MbSYNCHRONOUSDYNAMICRAM
PIN CONFIGURATIONS
50-PinTSOP(TypeII)
PINDESCRIPTIONS
A0-A11
AddressInput
A0-A10
RowAddressInput
A11
BankSelectAddress
A0-A7
ColumnAddressInput
DQ0toDQ15
DataDQ
CLK
SystemClockInput
CKE
ClockEnable
CS
ChipSelect
RAS
RowAddressStrobeCommand
CAS
ColumnAddressStrobeCommand
WE
WriteEnable
LDQM
LowerBye,Input/OutputMask
UDQM
UpperBye,Input/OutputMask
VDD
Power
VSS
Ground
VDDQ
PowerSupplyforDQPin
VSSQ
GroundforDQPin
NC
NoConnection
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9
10
11
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50
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26
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS


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