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IS45S16100F Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc

Part # IS45S16100F
Description  Random column address every clock cycle
Download  86 Pages
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS45S16100F Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc

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IS42/45S16100F, IS42VS16100F
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42S16100F and IS45S16100F AC CHARACTERISTICS(1,2,3)
-5
-6
-7
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Units
tck3
ClockCycleTime
CAS
Latency=3
5—
6—
7—
ns
tck2
CAS
Latency=2
10—
10—
10—
ns
tac3
AccessTimeFromCLK(4)
CAS
Latency=3
—5
—5.5
—5.5
ns
tac2
CAS
Latency=2
—6
—6
—6
ns
tchi
CLKHIGHLevelWidth
2—
2.5—
2.5—
ns
tcl
CLKLOWLevelWidth
2—
2.5—
2.5—
ns
toh3
OutputDataHoldTime
CAS
Latency=3
2—
2.0—
2.0—
ns
toh2
CAS
Latency=2
2.5—
2.5—
2.5—
ns
tlz
OutputLOWImpedanceTime
0—
0—
0—
ns
thz3
OutputHIGHImpedanceTime(5)
CAS
Latency=3
—5
—5.5
—5.5
ns
thz2
CAS
Latency=2
—6
—6
—6
ns
tds
InputDataSetupTime
2—
2—
2—
ns
tdh
InputDataHoldTime
1—
1—
1—
ns
tas
AddressSetupTime
2—
2—
2—
ns
tah
AddressHoldTime
1—
1—
1—
ns
tcks
CKESetupTime
2—
2—
2—
ns
tckh
CKEHoldTime
1—
1—
1—
ns
tcka
CKEtoCLKRecoveryDelayTime
1CLK+3 —
1CLK+3 —
1CLK+3 —
ns
tcs
CommandSetupTime(CS,RAS,CAS,WE,DQM)
2—
2—
2—
ns
tch
CommandHoldTime(CS,RAS,CAS,WE,DQM)
1—
1—
1—
ns
trc
CommandPeriod(REFtoREF/ACTtoACT)
50—
54—
63—
ns
tras
CommandPeriod(ACTtoPRE)
35 100,000
36 100,000
42 100,000 ns
trp
CommandPeriod(PREtoACT)
15—
18—
20—
ns
trcd
ActiveCommandToRead/WriteCommandDelayTime
15—
18—
20—
ns
trrd
CommandPeriod(ACT[0]toACT[1])
10—
12—
14—
ns
tdpl3
InputDataToPrecharge
CAS
Latency=3
2CLK —
2CLK—
2CLK—
ns
tdpl2
CommandDelaytime
CAS
Latency=2
2CLK —
2CLK—
2CLK—
ns
tdal3
InputDataToActive/Refresh
CAS
Latency=3
2CLK+trp
2CLK+trp
2CLK+trp
ns
tdal2
CommandDelaytime(DuringAuto-Precharge) CAS
Latency=2
2CLK+trp
2CLK+trp
2CLK+trp
ns
txsr
ExitSelf-RefreshtoActiveTime
55—
60—
70—
ns
tt
TransitionTime
0.31.2
0.31.2
0.31.2
ns
tref
RefreshCycleTime(2048)
—32
—32
—32
ms
Notes:
1.Whenpowerisfirstapplied,memoryoperationshouldbestarted100µsafterVdd andVddq reachtheirstipulatedvoltages.Alsonotethatthepower-on
sequencemustbeexecutedbeforestartingmemoryoperation.
2.measuredwithtt =1ns.Ifclockrisingtimeislongerthan1ns,(tt/2-0.5)nsshouldbeaddedtotheparameter.
3.Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming.RiseandfalltimesaremeasuredbetweenVih (min.)andVil (max.).
4.Accesstimeismeasuredat1.4Vwiththeloadshowninthefigurethatfollows.
5.Thetimethz (max.)isdefinedasthetimerequiredfortheoutputvoltagetotransitionby±200mVfromVoh (min.)orVol(max.)whenthe
outputisinthehighimpedancestate.


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