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IS42S16800F Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS42S16800F Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
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2 / 62 page  2 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 05/08/2012 IS42/45S81600F, IS42/45S16800F DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-accessmemorydesignedtooperatein3.3VVdd and3.3VVddq memorysystemscontaining134,217,728 bits.Internallyconfiguredasaquad-bankDRAMwitha synchronousinterface.Each33,554,432-bitbankisorga- nizedas4,096rowsby512columnsby16bitsor4,096 rowsby1,024columnsby8bits. The128MbSDRAMincludesanAUTOREFRESHMODE, andapower-saving,power-downmode.Allsignalsare registeredonthepositiveedgeoftheclocksignal,CLK. AllinputsandoutputsareLVTTLcompatible. The128MbSDRAMhastheabilitytosynchronouslyburst dataatahighdataratewithautomaticcolumn-address generation,theabilitytointerleavebetweeninternalbanks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burstaccess. Aself-timedrowprechargeinitiatedattheendoftheburst sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Prechargeonebankwhileaccessingoneofthe otherthreebankswillhidetheprechargecyclesandprovide seamless,high-speed,random-accessoperation. SDRAMreadandwriteaccessesareburstorientedstarting ataselectedlocationandcontinuingforaprogrammed number of locations in a programmed sequence.The registration of an ACTIVE command begins accesses, followedbyaREADorWRITEcommand.TheACTIVE commandinconjunctionwithaddressbitsregisteredare usedtoselectthebankandrowtobeaccessed(BA0, BA1selectthebank;A0-A11selecttherow).TheREAD or WRITE commands in conjunction with address bits registeredareusedtoselectthestartingcolumnlocation fortheburstaccess. ProgrammableREADorWRITEburstlengthsconsistof 1,2,4and8locationsorfullpage,withaburstterminate option. CLK CKE CS RAS CAS WE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 A10 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER REFRESH CONTROLLER REFRESH COUNTER SELF REFRESH CONTROLLER ROW ADDRESS LATCH COLUMN ADDRESS LATCH BURST COUNTER COLUMN ADDRESS BUFFER COLUMN DECODER DATA IN BUFFER DATA OUT BUFFER DQML DQMH DQ 0-15 VDD/VDDQ Vss/VssQ 12 12 9 12 12 9 16 16 16 16 512 (x 16) 4096 4096 4096 4096 MEMORY CELL ARRAY BANK 0 SENSE AMP I/O GATE BANK CONTROL LOGIC ROW ADDRESS BUFFER A11 2 FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONlY) |
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