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IS46LR32800G-6BLA1 Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS46LR32800G-6BLA1 Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc |
7 / 47 page IS43LR32800G, IS46LR32800G 7 Rev. A | November 2013 www.issi.com - dram@issi.com Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 3. M3 Burst Type 0 Sequential 1 Interleave M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M2 M1 M0 Burst Length M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 16 16 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Address Bus A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Figure 5 : Mode Register Set (MRS) Definition BA0 BA1 14 13 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CAS Latency BT Burst Length Note: M14(BA1) = 0 and M13(BA0) = 0 to select Mode Register Mode Register (Mx) |
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