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IS49FL004T-33JCE Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS49FL004T-33JCE Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
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10 / 45 page  IS49FL004T Integrated Silicon Solution, Inc.- www.issi.com 10 Rev. A1 9/19/2013 FWH MODE OPERATION (CONTINUED) Table 3: FWH Memory Write Cycle Definition Clock Cycle Field FWH[3:0] Direction Description 1 START 1110 IN Start of Cycle: "1110b" to indicate the start of a memory write cycle. 2 IDSEL 0000 to 1111 IN ID Select Cycle: Indicates which FWH device should respond. If the IDSEL field matches the value set on ID[3:0] pins, then the particular FWH device will respond to subsequent commands. 3-9 IMADDR YYYY IN Address Cycles: This is the 28-bit memory address. The addresses transfer most-significant nibble first and least- significant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and A3 - A0 on FWH[3:0] last). 10 IMSIZE 0000 IN Memory Size Cycle: Indicates how many bytes will be or transferred during multi-byte operations. The IS49FL00x only support "0000b" for one byte operation. 11-12 DATA YYYY IN Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last). 13 TAR0 1111 IN then Float Turn-Around Cycle 0: The Intel ICH has driven the bus then float it to all "1"s and then floats the bus. 14 TAR1 1111 (float) Float then OUT Turn-Around Cycle 1: The device takes control of the bus during this cycle. 15 RSYNC 0000 (READY) OUT Ready Sync: The FWH device indicates that it has received the data or command. 16 TAR0 1111 OUT then Float Turn-Around Cycle 0: The FWH device has driven the bus then float it to all "1"s and then floats the bus. 17 TAR1 1111 (float) Float then IN Turn-Around Cycle 1: The Intel ICH resumes control of the bus during this cycle. FWH MEMORY WRITE CYCLE WAVEFORMS CL K RST# or INIT# F W H 4 Memory Write Start IDSEL FWH[3:0] 1110b ID[3:0] xxxxb x1xxb Address A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] IMSIZE 0000b D[3:0] Data D[7:4] TAR R SYN C 1111b Tri-State 0000b TAR 1111b Tri-State Next Start 1110b 1 Clock 1 Clock Load Address in 7 Clocks 1 Clock Load Data in 2 Clocks 2 Clocks 1 Clock 2 Clocks 1 Clock From Host to Device From Device to Host |
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