IS61DDB44M18A

IS61DDB42M36A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

12/08/2014

10

State Diagram

Power-Up

NOP

Load New Read Address

D count = 0

DDR-II Read

D count =

D count +1

DDR-II Write

D count =

D count +1

Increment Read

Address

Increment Write

Address

Load

Load

Load

Read

Write

Read

D count = 1

Write

D count = 1

Always

Always

/LOAD

D count = 2

/LOAD

D count = 2

/LOAD

Notes:

1.

Internal burst counter is fixed as four-bit linear; that is when first address is A0+0, next internal burst addresses are A0+1, A0+2, and A0+3

2.

Read refers to read active status with R/W# = High.

3.

Write refers to write active status with R/W# = LOW.

4.

Load refers to read new address active status with LD# = low.

5.

Load is read new address inactive status with LD = high.

Linear Burst Sequence Table

Burst Sequence

Case1

Case2

Case3

Case4

First Address

0

0

0

1

1

0

1

1

Second Address

0

1

1

0

1

1

0

0

Third Address

1

0

1

1

0

0

0

1

Fourth Address

1

1

0

0

0

1

1

0