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IS61DDPB24M18B2 Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS61DDPB24M18B2 Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
10 / 31 page IS61DDPB24M18B/B1/B2 IS61DDPB22M36B/B1/B2 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/11/2014 10 Application Example The following figure depicts an implementation of four 4M x 18 DDR-IIP SRAMs with common I/Os. SRAM #1 SA R/W# LD# BWx# K/K# DQ CQ/CQ# ZQ RQ = 250 Ω SRAM #4 ZQ RQ = 250 Ω Data-In&Data Out Address SRAM #1 CQ Input SRAM #4 CQ Input Read&Write Control New Address Control Byte Write Control Source CLK Memory Controller Vt Vt R R = 50 Ω R Vt = V REF SA R/W# LD# BWx# K/K# DQ CQ/CQ# Vt R |
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