IS61DDPB42M18B/B1/B2

IS61DDPB41M36B/B1/B2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

9/25/2014

3

Ball Descriptions

Symbol

Type

Description

K, K#

Input

Input clock: This input clock pair registers address and control inputs on the rising edge of K, and

registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of

phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.

These balls cannot remain VREF level.

CQ, CQ#

Output

Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals are free running clocks and

do not stop when Q tri-states.

Doff#

Input

DLL disable and reset input : When low, this input causes the DLL to be bypassed and reset the

previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock

time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the

device can be operated at a frequency of up to 167 MHz.

QVLD

Output

Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

CQ#.

SA

Input

Synchronous address inputs: These inputs are registered and must meet the setup and hold times

around the rising edge of K. These inputs are ignored when device is deselected.

DQ0 - DQn

Bidir

Data input and output signals. Input data must meet setup and hold times around the rising edges of

K and K# during WRITE operations. These pins drive out the requested data when the read

operation is active. Valid output data is synchronized to the respective CQ and CQ#.

See BALL CONFIGURATION figures for ball site location of individual signals.

The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin.

The x36 device uses DQ0~DQ35.

R/W#

Input

Synchronous Read or Write input. When LD# is low, this input designates the access type (read

when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times

around edge of K.

LD#

Input

Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition

includes address and read/write direction.

Input

Synchronous byte writes: When low, these inputs cause their respective byte to be registered and

written during WRITE cycles. These signals are sampled on the same edge as the corresponding

data and must meet setup and hold times around the rising edges of K and K# for each of the two

rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.

Input

reference

HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise

margin. Provides a reference voltage for the HSTL input buffers.

Power

Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.

Power

Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating

Conditions for range.

Ground

Ground of the device

ZQ

Input

Output impedance matching input: This input is used to tune the device outputs to the system data

bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this ball

to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance

mode. This ball cannot be connected directly to VSS or left unconnected.

In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.

The ODT range is selected by ODT control input.

TMS, TDI, TCK

Input

IEEE 1149.1 input pins for JTAG

TDO

Output

IEEE 1149.1 output pins for JTAG

NC

N/A

No connect: These signals should be left floating or connected to ground to improve package heat

dissipation.

ODT

Input

ODT control; Refer to SRAM features for the details.