Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. A

09/29/2011

Copyright©2011IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithout

notice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersareadvisedtoobtainthelat-

estversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.

IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreason-

ablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenotauthorizedforuseinsuchapplications

unlessIntegratedSiliconSolution,Inc.receiveswrittenassurancetoitssatisfaction,that:

a.)theriskofinjuryordamagehasbeenminimized;

b.)theuserassumeallsuchrisks;and

c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances

IS61WV25616EDBLL

IS64WV25616EDBLL

FEATURES

• High-speedaccesstime:8,10ns

• LowActivePower:85mW(typical)

• LowStandbyPower:7mW(typical)

CMOSstandby

• Singlepowersupply

• Fullystaticoperation:noclockorrefresh

required

• Threestateoutputs

• Datacontrolforupperandlowerbytes

• IndustrialandAutomotivetemperaturesupport

• Lead-freeavailable

• ErrorDetectionandErrorCorrection

256K x 16 HIGH SPEED ASYNCHRONOUS

CMOS STATIC RAM WITH ECC

DESCRIPTION

The

4,194,304-bit static RAMs organized as 262,144 words

by16bits.Itisfabricatedusing

CMOS technology.This highly reliable process coupled

with innovative circuit design techniques, yields high-

performanceandlowpowerconsumptiondevices.

When CE is HIGH (deselected), the device assumes a

standbymodeatwhichthepowerdissipationcanbere-

duceddownwithCMOSinputlevels.

EasymemoryexpansionisprovidedbyusingChipEnable

andOutputEnableinputs,CEandOE.TheactiveLOW

WriteEnable(WE)controlsbothwritingandreadingofthe

memory.AdatabyteallowsUpperByte(UB)andLower

Byte(LB)access.

TheIS61/64WV25616EDBLLispackagedintheJEDEC

standard44-pinTSOP-IIand48-pinMiniBGA(6mmx

8mm).

FUNCTIONAL BLOCK DIAGRAM

OCTOBER 2011

Memory

Lower IO

Array-

256Kx8

ECC

Array-

256K

x4

Decoder

I/O Data

Circuit

ECC

Column I/O

IO0-7

Control

Circuit

A0-A17

IO8-15

8

ECC

8

8

8

12

12

Memory

Upper IO

Array-

256Kx8

ECC

Array-

256K

x4

8

4

4

8

/CE

/OE

/WE

/UB

/LB