IS62WV10248EALL/BLL

IS65WV10248EALL/BLL

1

Rev. B

10/21/2014

1Mx8 LOW VOLTAGE,

ULTRA LOW POWER CMOS STATIC RAM

KEY FEATURES



High-speed access time: 45ns, 55ns



CMOS low power operation

– 36 mW (typical) operating

– 12 µW (typical) CMOS standby



TTL compatible interface levels



Single power supply



Data control for upper and lower bytes



Automotive temperature (-40



Lead-free available

DESCRIPTION

The ISSI IS62WV10248EALL/ IS62WV10248EBLL are

high-speed, 8M bit static RAMs organized as 1M words

by 8 bits. It is fabricated using ISSI's high-performance

CMOS technology. This highly reliable process

coupled with innovative circuit design techniques,

yields high-performance and low power consumption

devices.

When

is HIGH (deselected) or when CS2 is low

(deselected), the device assumes a standby mode at

which the power dissipation can be reduced down with

CMOS input levels.

Easy memory expansion is provided by using Chip

Enable and Output Enable inputs. The active LOW

Write Enable (

) controls both writing and reading of

the memory.

The IS62WV10248EALL and IS62WV10248EBLL are

packaged in the JEDEC standard 48-pin mini BGA

(6mm x 8mm) and 44-Pin TSOP (TYPE II).

BLOCK DIAGRAM

Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

NOVEMBER 2014