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IS65WV102416DBLL Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS65WV102416DBLL Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
2 / 15 page IS62/65WV102416DALL IS62/65WV102416DBLL Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A 12/12/2014 48-PIN TSOP-I A15 1 48 A16 A14 2 47 A13 3 46 Vss A12 4 45 I/O15/A20 A11 5 44 I/O7 A10 6 43 I/O14 A9 7 42 I/O6 A8 8 41 I/O13 A19 9 40 I/O5 NC 10 39 I/O12 11 38 I/O4 CS2 12 37 Vcc NC 13 36 I/O11 14 35 I/O3 15 34 I/O10 A18 16 33 I/O2 A17 17 32 I/O9 A7 18 31 I/O1 A6 19 30 I/O8 A5 20 29 I/O0 A4 21 28 A3 22 27 Vss A2 23 26 A1 24 25 A0 PIN DESCRIPTIONS A0-A19 Address Inputs I/O0-I/O14 Data Inputs/Outputs, I/O8 to I/O14 pins are not used in x8 Mode. I/O15/A20 I/O15, when used in a x16 Mode. A20 when used in a x8 Mode, , CS2 Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7). This pin is not used in x8 Mode. Upper-byte Control (I/O8-I/O15). This pin is not used in x8 Mode. pin must be tied to either VDD to use the device as a 1024Kx16 SRAM or GND to use as 2048Kx8 SRAM. In x8 mode, Pin 45 becomes A20, while , and I/O8 to I/O14 pins are not used. NC No Connection VDD Power Vss Ground *For x8/x16 switchable configuration BGA option, please contact sram@issi.com |
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