IS66WVC1M16ALL datasheet(6/67 Pages) ISSI

Part #	IS66WVC1M16ALL

Description	Mixed Mode supports asynchronous write and synchronous read operation

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

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IS66WVC1M16ALL

IS67WVC1M16ALL

6

Rev.A | October 2013

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Notes

1. CLK must be LOW during Async Read and Async Write modes. CLK must be LOW to achieve

low standby current during standby mode and DPD modes. CLK must be static (LOW or HIGH)

during burst suspend.

2. Configuration registers are accessed when CRE is HIGH during the address portion

of a READ or WRITE cycle.

3. WAIT polarity is configured through the bus configuration register (BCR[10]).

4. When UB# and LB# are in select mode (LOW), DQ0~DQ15 are affected as shown.

When only LB# is in select mode, DQ0~DQ7 are affected as shown. When only UB# is

in select mode, DQ8~DQ15 are affected as shown.

5. The device will consume active power in this mode whenever addresses are changed

6. When the device is in standby mode, address inputs and data inputs/outputs are internally

isolated from any external influence.

7. Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current.

8. Burst mode operation is initialized through the bus configuration register (BCR[15]).

9. Byte operation can be supported Write & Read at asynchronous mode and Write at

synchronous mode.

10. DPD is initiated when CE# transition from LOW to HIGH after writing RCR[4] to 0. DPD is

maintained until CE# transitions from HIGH to LOW

11. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW

for the equivalent of a single word burst (as indicated by WAIT).

12. When the BCR is configured for sync mode, sync READ and sync WRITE and async WRITE

are supported.

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