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IS67WVE1M16EALL Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS67WVE1M16EALL Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
10 / 32 page 10 IS66WVE1M16EALL/BLL/CLL IS67WVE1M16EALL/BLL/CLL Rev. 0D | November 2014 www.issi.com - SRAM@issi.com Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is preformed, then adjacent addresses can be read quickly by simply changing the low- order address. Addresses A[3:0] are used to determine the members of the 16-address PSRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time. Figure 4 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read faster than random addresses. WRITE operations do not include comparable page mode functionality. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. UB#/LB# Operation The UB#/LB# enable signals accommodate byte-wide data transfers. During READ operations, enabled bytes are driven onto the DQ. The DQ signals associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, disabled bytes are not transferred to the memory array. and the internal value remains unchanged. During a WRITE cycle the data to be written is latched on the rising edge of CE#, WE#, LB# or UB#, whichever occurs first. When both the UB#/LB# are disabled (HIGH) during an operation, the device prevents the data bus from receiving or transmitting data. Although the device may appear to be deselected, it remains in active mode as long as CE# remains LOW. Figure 4. Page Mode READ Operation Address DQ0- DQ15 CE# UB#/LB# OE# WE# tAA ADD3 ADD2 ADD1 ADD0 D0 D1 D2 D3 tAPA tAPA tAPA < tCEM |
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