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IS67WVE4M16BLL Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS67WVE4M16BLL Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc |
7 / 32 page 7 IS66WVE4M16EALL/BLL/CLL IS67WVE4M16EALL/BLL/CLL Rev.0B | November 2014 www.issi.com - SRAM@issi.com Functional Description In general, this device is high-density alternatives to SRAM and Pseudo SRAM products popular in low-power, portable applications. The 64Mb device contains a 64Mb DRAM core organized as 4,194,304 addresses by 16 bits. This device include the industry-standard, asynchronous memory interface found on other low-power SRAM or PSRAM offerings Page mode access is also supported as a bandwidth-enhancing extension to the asynchronous read protocol. Power-Up Initialization PSRAM products include an on-chip voltage sensor that is used to launch the power-up initialization process. Initialization will load the CR with its default settings (see Table 3). VDD and VDDQ must be applied simultaneously. When they reach a stable level above VDD, the device will require 150μs to complete its self-initialization process ( see Figure 1). During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 1: Power-Up Initialization Timing VDD Device Initialization tPU > 150us Device ready for normal operation VDD VDDQ |
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