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SN74LV4051ADGVRG4 Datasheet(PDF) 3 Page - Texas Instruments |
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SN74LV4051ADGVRG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 33 page 1 16 8 9 2 3 4 5 6 7 15 14 13 12 11 10 Y2 Y1 Y0 Y3 A B Y6 COM Y7 Y5 INH GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Y4 Y6 COM Y7 Y5 INH GND GND VCC Y2 Y1 Y0 Y3 A B SN74LV4051A www.ti.com SCLS428I – MAY 1999 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions D, DB, DGB, N, NS, PW Package RGY Package 16-Pin SOIC, SSOP, TVSOP, PDIP, SO, TSSOP 16-Pin VQFN With Exposed Thermal Pad Top View Top View Pin Functions PIN I/O DESCRIPTION NAME NO. A 11 I Selector line A for outputs (see Device Functional Modes for specific information) B 10 I Selector line B for outputs (see Device Functional Modes for specific information) C 9 I Selector line C for outputs (see Device Functional Modes for specific information) COM 3 O/I(1) Output/Input of mux GND 7, 8 — Ground Enables the outputs of the device. Logic low level with turn the outputs on, high level will turn INH 6 I(1) them off. Y0 13 I/O(1) Input/Output to mux Y1 14 I/O(1) Input/Output to mux Y2 15 I/O(1) Input/Output to mux Y3 12 I/O(1) Input/Output to mux Y4 1 I/O(1) Input/Output of mux Y5 5 I/O(1) Input/Output to mux Y6 2 I/O(1) Input/Output to mux Y7 4 I/O(1) Input/Output to mux VCC 16 — Device power (1) These I/O descriptions represent the device when used as a multiplexer, when this device is operated as a demultiplexer pins Y0-Y7 may be considered outputs (O) and the COM pin may be considered inputs (I). Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN74LV4051A |
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