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ADC12H030CIWM Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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ADC12H030CIWM Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 41 page AC Electrical Characteristics (Continued) The following specifications apply for V + =V A+=VD+ = +5.0 VDC,VREF+ = +4.096 VDC,VREF−=0 VDC, 12-bit + sign conver- sion mode, t r =tf = 3 ns, fCK =fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK =fSK =5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =25 Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Bold- face limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17) Symbol Parameter Conditions Typical (Note 10) ADC12H030/2/4/8 ADC12030/2/4/8 Units (Limits) Limits Limits (Note 11) (Note 11) t A Acquisition Time 6 Cycles Programmed 6(t CK) 6(t CK) 6(t CK) (min) (Note 19) 7(t CK) 7(t CK) (max) 0.75 1.2 µs (min) 0.875 1.4 µs (max) 10 Cycles Programmed 10(t CK) 10(t CK) 10(t CK) (min) 11(t CK) 11(t CK) (max) 1.25 2.0 µs (min) 1.375 2.2 µs (max) 18 Cycles Programmed 18(t CK) 18(t CK) 18(t CK) (min) 19(t CK) 19(t CK) (max) 2.25 3.6 µs (min) 2.375 3.8 µs (max) 34 Cycles Programmed 34(t CK) 34(t CK) 34(t CK) (min) 35(t CK) 35(t CK) (max) 4.25 6.8 µs (min) 4.375 7.0 µs (max) t CKAL Self-Calibration Time 4944(t CK) 4944(t CK) 4944(t CK) (max) 618.0 988.8 µs (max) t AZ Auto-Zero Time 76(t CK) 76(t CK) 76(t CK) (max) 9.5 15.2 µs (max) t SYNC Self-Calibration 2(t CK) 2(t CK) 2(t CK) (min) or Auto-Zero 3(t CK) 3(t CK) (max) Synchronization Time 0.250 0.40 µs (min) from DOR 0.375 0.60 µs (max) t DOR DOR High Time 9(t SK) 9(t SK) 9(t SK) (max) when CS is Low 1.125 1.8 µs (max) Continuously for Read Data and Software Power Up/Down t CONV CONV Valid Data Time 8(t SK) 8(t SK) 8(t SK) (max) 1.0 1.6 µs (max) AC Electrical Characteristics The following specifications apply for V + =V A+=VD+ = +5.0 VDC,VREF+ = +4.096 VDC,VREF−=0 VDC, 12-bit + sign conver- sion mode, t r =tf = 3 ns, fCK =fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK =fSK =5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S =25 Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Bold- face limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) t HPU Hardware Power-Up Time, Time from 140 250 µs (max) PD Falling Edge to EOC Rising Edge t SPU Software Power-Up Time, Time from Serial Data Clock Falling Edge to 140 250 µs (max) www.national.com 9 |
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