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ADC34J25IRGZ25 Datasheet(PDF) 5 Page - Texas Instruments |
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ADC34J25IRGZ25 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 88 page  ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage range, AVDD –0.3 2.1 V Supply voltage range, DVDD –0.3 2.1 V Minimum INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM –0.3 V (AVDD + 0.3, 2.1) Minimum CLKP, CLKM(2) –0.3 V Voltage applied to input (AVDD + 0.3, 2.1) pins: Minimum SYSREFP, SYSREFM, SYNCP~, SYNCM~ –0.3 V (AVDD + 0.3, 2.1) SCLK, SEN, SDATA, RESET, PDN –0.3 3.6 V Operating free-air, TA –40 85 °C Temperature Operating junction, TJ 125 °C Storage, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage range 1.7 1.8 1.9 V DVDD Digital supply voltage range 1.7 1.8 1.9 V ANALOG INPUT For input frequencies < 450 MHz 2 VPP VID Differential input voltage For input frequencies < 600 MHz 1 VPP VIC Input common-mode voltage VCM ± 0.025 V CLOCK INPUT Input clock frequency Sampling clock frequency 25 160(2) MSPS Sine wave, ac-coupled 0.2 1.5 V Input clock amplitude (differential) LPECL, ac-coupled 1.6 V LVDS, ac-coupled 0.7 V Input clock duty cycle 35 50 65 % Input clock common-mode voltage 0.95 V DIGITAL OUTPUTS Maximum external load capacitance CLOAD 3.3 pF from each output pin to GND RLOAD Single-ended load resistance 100 Ω (1) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section. (2) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 |
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