Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

ADN2917ACPZ Datasheet(PDF) 5 Page - Analog Devices

Part # ADN2917ACPZ
Description  Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
Download  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADN2917ACPZ Datasheet(HTML) 5 Page - Analog Devices

  ADN2917ACPZ Datasheet HTML 1Page - Analog Devices ADN2917ACPZ Datasheet HTML 2Page - Analog Devices ADN2917ACPZ Datasheet HTML 3Page - Analog Devices ADN2917ACPZ Datasheet HTML 4Page - Analog Devices ADN2917ACPZ Datasheet HTML 5Page - Analog Devices ADN2917ACPZ Datasheet HTML 6Page - Analog Devices ADN2917ACPZ Datasheet HTML 7Page - Analog Devices ADN2917ACPZ Datasheet HTML 8Page - Analog Devices ADN2917ACPZ Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 32 page
background image
Data Sheet
ADN2917
Rev. A | Page 5 of 32
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
8GFC,3 JTSPAT
Sinusoidal Jitter at 340 kHz
6.7
UI p-p
Sinusoidal Jitter at 5.098 MHz
0.53
UI p-p
Sinusoidal Jitter at 80 MHz
0.59
UI p-p
Rx Jitter Tracking Test4
Voltage modulation amplitude (VMA) = 170 mV p-p at
100 MHz, 425 mV p-p at 100 MHz, 170 mV p-p at 2.5 GHz,
and 425 mV p-p at 2.5 GHz excitation frequency5
510 kHz, 1 UI
10−12
<10−12
BER
100 kHz, 5 UI
10−12
<10−12
BER
1
Jitter transfer bandwidth is programmable by adjusting TRANBW[2:0] in the DPLLA register (Register 0x10).
2
Set TRANBW[2:0] (Bits[D2:D0] in Register 0x10) = 1 to enter OTN mode. OTN is the optical transport network as defined in ITU G.709.
3
Fibre Channel Physical Interface 4 standard, FC-PI-4, Rev 8.00, May 21, 2008.
4
Conditions of FC-PI-4, Rev 8.00, Table 27, 800-DF-EL-S apply.
5
Must have zero errors during the tests for an interval of time that is ≤10−12 BER to pass the tests.
OUTPUT AND TIMING SPECIFICATIONS
TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data
pattern: PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CML OUTPUT CHARACTERISTICS
Data Differential Output Swing
OC-192, DATA_SWING[3:0] (Bits[D7:D4] in
Register 0x1F) setting = 0xC (default)
535
600
672
mV p-p
OC-192, DATA_SWING[3:0] setting = 0xF (maximum)
668
724
771
mV p-p
OC-192, DATA_SWING[3:0] setting = 0x4 (minimum)
189
219
252
mV p-p
Clock Differential Output Swing
OC-192, CLOCK_SWING[3:0] (Bits[D3:D0] in
Register 0x1F) setting = 0xC (default)
406
508
570
mV p-p
OC-192, CLOCK_SWING[3:0] setting = 0xF (maximum)
448
583
659
mV p-p
OC-192, CLOCK_SWING[3:0] setting = 0x4 (minimum)
162
217
249
mV p-p
Data Differential Output Swing
8GFC, DATA_SWING[3:0] setting = 0xC (default)
540
600
666
mV p-p
8GFC, DATA_SWING[3:0] setting = 0xF (maximum)
662
725
778
mV p-p
8GFC, DATA_SWING[3:0] setting = 0x4 (minimum
190
214
245
mV p-p
Clock Differential Output Swing
8GFC, CLOCK_SWING[3:0] setting = 0xC (default)
426
518
588
mV p-p
8GFC, CLOCK_SWING[3:0] setting = 0xF (maximum)
489
603
680
mV p-p
8GFC, CLOCK_SWING[3:0] setting = 0x4 (minimum)
166
213
245
mV p-p
Output High Voltage
VOH, dc-coupled
VCC – 0.05
VCC −
0.025
VCC
V
Output Low Voltage
VOL, dc-coupled
VCC – 0.36
VCC −
0.325
VCC −
0.29
V
CML OUTPUT TIMING CHARACTERISTICS
Rise Time
20% to 80%, at OC-192, DATOUTN/DATOUTP
17.4
32.6
46.5
ps
20% to 80%, at OC-192, CLKOUTN/CLKOUTP
22.2
28.3
33.1
ps
20% to 80%, at 8GFC,1 DATOUTN/DATOUTP
20.4
33.1
44
ps
20% to 80%, at 8GFC,1 CLKOUTN/CLKOUTP
23.1
29.7
35.8
ps
Fall Time
80% to 20%, at OC-192, DATOUTN/DATOUTP
17.5
33
49.1
ps
80% to 20%, at OC-192, CLKOUTN/CLKOUTP
23.9
29.2
33.7
ps
80% to 20%, at 8GFC,1 DATOUTN/DATOUTP
23
34.2
46.8
ps
80% to 20%, at 8GFC,1 CLKOUTN/CLKOUTP
25
31.3
37.1
ps
Setup Time, Full Rate Clock
tS (see Figure 2)
0.5
UI
Hold Time, Full Rate Clock
tH (see Figure 2)
0.5
UI
Setup Time, DDR Clock
tS (see Figure 3)
0.5
UI
Hold Time, DDR clock
tH (see Figure 3)
0.5
UI


Similar Part No. - ADN2917ACPZ

ManufacturerPart #DatasheetDescription
logo
Analog Devices
ADN2913 AD-ADN2913 Datasheet
577Kb / 37P
   Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
ADN2913ACPZ AD-ADN2913ACPZ Datasheet
577Kb / 37P
   Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
ADN2913ACPZ-RL7 AD-ADN2913ACPZ-RL7 Datasheet
577Kb / 37P
   Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
ADN2915 AD-ADN2915 Datasheet
776Kb / 36P
   Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
ADN2915ACPZ AD-ADN2915ACPZ Datasheet
776Kb / 36P
   Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
More results

Similar Description - ADN2917ACPZ

ManufacturerPart #DatasheetDescription
logo
Analog Devices
ADN2915 AD-ADN2915 Datasheet
776Kb / 36P
   Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
ADN2913 AD-ADN2913 Datasheet
577Kb / 37P
   Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
logo
Texas Instruments
ONET8501PB TI1-ONET8501PB Datasheet
1Mb / 27P
[Old version datasheet]   11.3-Gbps RATE-SELECTABLE LIMITING AMPLIFIER
ONET8501P TI-ONET8501P Datasheet
1Mb / 26P
[Old version datasheet]   11.3-Gbps RATE-SELECTABLE LIMITING AMPLIFIER
ONET8501PB TI1-ONET8501PB_17 Datasheet
1Mb / 32P
[Old version datasheet]   11.3-Gbps Rate-Selectable Limiting Amplifier
logo
Analog Devices
ADN2814 AD-ADN2814 Datasheet
336Kb / 28P
   Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
Rev. PrA
ADN2813 AD-ADN2813 Datasheet
522Kb / 28P
   Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
REV. 0
ADN2812 AD-ADN2812 Datasheet
478Kb / 28P
   Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
REV. 0
ADN2818 AD-ADN2818_15 Datasheet
813Kb / 40P
   Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs
Rev. E
ADN2817 AD-ADN2817_15 Datasheet
813Kb / 40P
   Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs
Rev. E
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com