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ADN2917ACPZ Datasheet(PDF) 5 Page - Analog Devices |
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ADN2917ACPZ Datasheet(HTML) 5 Page - Analog Devices |
5 / 32 page Data Sheet ADN2917 Rev. A | Page 5 of 32 Parameter Test Conditions/Comments Min Typ Max Unit 8GFC,3 JTSPAT Sinusoidal Jitter at 340 kHz 6.7 UI p-p Sinusoidal Jitter at 5.098 MHz 0.53 UI p-p Sinusoidal Jitter at 80 MHz 0.59 UI p-p Rx Jitter Tracking Test4 Voltage modulation amplitude (VMA) = 170 mV p-p at 100 MHz, 425 mV p-p at 100 MHz, 170 mV p-p at 2.5 GHz, and 425 mV p-p at 2.5 GHz excitation frequency5 510 kHz, 1 UI 10−12 <10−12 BER 100 kHz, 5 UI 10−12 <10−12 BER 1 Jitter transfer bandwidth is programmable by adjusting TRANBW[2:0] in the DPLLA register (Register 0x10). 2 Set TRANBW[2:0] (Bits[D2:D0] in Register 0x10) = 1 to enter OTN mode. OTN is the optical transport network as defined in ITU G.709. 3 Fibre Channel Physical Interface 4 standard, FC-PI-4, Rev 8.00, May 21, 2008. 4 Conditions of FC-PI-4, Rev 8.00, Table 27, 800-DF-EL-S apply. 5 Must have zero errors during the tests for an interval of time that is ≤10−12 BER to pass the tests. OUTPUT AND TIMING SPECIFICATIONS TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern: PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit CML OUTPUT CHARACTERISTICS Data Differential Output Swing OC-192, DATA_SWING[3:0] (Bits[D7:D4] in Register 0x1F) setting = 0xC (default) 535 600 672 mV p-p OC-192, DATA_SWING[3:0] setting = 0xF (maximum) 668 724 771 mV p-p OC-192, DATA_SWING[3:0] setting = 0x4 (minimum) 189 219 252 mV p-p Clock Differential Output Swing OC-192, CLOCK_SWING[3:0] (Bits[D3:D0] in Register 0x1F) setting = 0xC (default) 406 508 570 mV p-p OC-192, CLOCK_SWING[3:0] setting = 0xF (maximum) 448 583 659 mV p-p OC-192, CLOCK_SWING[3:0] setting = 0x4 (minimum) 162 217 249 mV p-p Data Differential Output Swing 8GFC, DATA_SWING[3:0] setting = 0xC (default) 540 600 666 mV p-p 8GFC, DATA_SWING[3:0] setting = 0xF (maximum) 662 725 778 mV p-p 8GFC, DATA_SWING[3:0] setting = 0x4 (minimum 190 214 245 mV p-p Clock Differential Output Swing 8GFC, CLOCK_SWING[3:0] setting = 0xC (default) 426 518 588 mV p-p 8GFC, CLOCK_SWING[3:0] setting = 0xF (maximum) 489 603 680 mV p-p 8GFC, CLOCK_SWING[3:0] setting = 0x4 (minimum) 166 213 245 mV p-p Output High Voltage VOH, dc-coupled VCC – 0.05 VCC − 0.025 VCC V Output Low Voltage VOL, dc-coupled VCC – 0.36 VCC − 0.325 VCC − 0.29 V CML OUTPUT TIMING CHARACTERISTICS Rise Time 20% to 80%, at OC-192, DATOUTN/DATOUTP 17.4 32.6 46.5 ps 20% to 80%, at OC-192, CLKOUTN/CLKOUTP 22.2 28.3 33.1 ps 20% to 80%, at 8GFC,1 DATOUTN/DATOUTP 20.4 33.1 44 ps 20% to 80%, at 8GFC,1 CLKOUTN/CLKOUTP 23.1 29.7 35.8 ps Fall Time 80% to 20%, at OC-192, DATOUTN/DATOUTP 17.5 33 49.1 ps 80% to 20%, at OC-192, CLKOUTN/CLKOUTP 23.9 29.2 33.7 ps 80% to 20%, at 8GFC,1 DATOUTN/DATOUTP 23 34.2 46.8 ps 80% to 20%, at 8GFC,1 CLKOUTN/CLKOUTP 25 31.3 37.1 ps Setup Time, Full Rate Clock tS (see Figure 2) 0.5 UI Hold Time, Full Rate Clock tH (see Figure 2) 0.5 UI Setup Time, DDR Clock tS (see Figure 3) 0.5 UI Hold Time, DDR clock tH (see Figure 3) 0.5 UI |
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