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AD7298-1 Datasheet(PDF) 5 Page - Analog Devices

Part # AD7298-1
Description  8-Channel, 1 MSPS, 10-Bit SAR ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7298-1 Datasheet(HTML) 5 Page - Analog Devices

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AD7298-1
Rev. A | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 2.8 V to 3.6 V, VDRIVE = 1.65 V to 3.6 V, VREF = 2.5 V internal, TA = −40°C to +125°C, unless otherwise noted. Sample tested during
initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level
of 1.6 V.
Table 2.
Parameter
Limit at T
MIN, TMAX
Unit
Test Conditions/Comments
t
CONVERT
t
2 + (16 × tSCLK)
µs max
Conversion time
820
ns typ
Each ADC channel V
IN0 to VIN7, fSCLK = 20 MHz
f
SCLK
1
50
kHz min
Frequency of external serial clock
20
MHz max
Frequency of external serial clock
t
QUIET
6
ns min
Minimum quiet time required between the end of the serial read and the start of
the next voltage conversion in repeat and nonrepeat mode.
t
2
10
ns min
CS to SCLK setup time
t
3
1
15
ns max
Delay from CS (falling edge) until DOUT three-state disabled
t
4
1
Data access time after SCLK falling edge
35
ns max
V
DRIVE = 1.65 V to 3 V
28
ns max
V
DRIVE = 3 V to 3.6 V
t
5
0.4 × t
SCLK
ns min
SCLK low pulse width
t
6
0.4 × t
SCLK
ns min
SCLK high pulse width
t
7
1
14
ns min
SCLK to DOUT valid hold time
t
8
1
16/34
ns min/ns max
SCLK falling edge to DOUT high impedance
t
9
5
ns min
DIN setup time prior to SCLK falling edge
t
10
4
ns min
DIN hold time after SCLK falling edge
t
11
1
30
ns max
Delay from CS rising edge to DOUT high impedance
t
POWER-UP
6
ms max
Internal reference power-up time from full power-down
1 Measured with a load capacitance on DOUT of 15 pF.


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