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AD9635BCPZRL7-125 Datasheet(PDF) 8 Page - Analog Devices |
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AD9635BCPZRL7-125 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 36 page  AD9635 Data Sheet Rev. B | Page 8 of 36 Figure 4. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode Figure 5. 10-Bit DDR/SDR, Two-Lane, 2× Frame Mode D0A– D0A+ D1A– D1A+ FCO– BYTEWISE MODE FCO+ D0A– D0A+ D1A– D1A+ FCO– DCO– CLK+ CLK– DCO+ FCO+ BITWISE MODE SDR DDR DCO– DCO+ D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 MSB N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 MSB N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 MSB N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 MSB N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D06 N – 17 tEH tCPD tFRAME tFCO tPD tDATA tLD tEL VINx± tA N – 1 N N + 1 D0A– D0A+ D1A– D1A+ FCO– BYTEWISE MODE FCO+ D0A– D0A+ D1A– D1A+ FCO– DCO– CLK+ CLK– DCO+ FCO+ BITWISE MODE SDR DDR DCO– DCO+ D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 MSB N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 MSB N – 17 D08 N – 17 D07 N – 17 D06 N – 17 D05 N – 17 tEH tCPD tFRAME tFCO tPD tDATA tLD tEL VINx± tA N – 1 N N + 1 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 D08 N – 15 D06 N – 15 D04 N – 15 D02 N – 15 LSB N – 16 MSB N – 16 D07 N – 15 D05 N – 15 D03 N – 15 MSB N – 15 D01 N – 17 D04 N – 16 D03 N – 15 D02 N – 15 D01 N – 15 D04 N – 15 MSB N – 16 D08 N – 16 D07 N – 16 D06 N – 16 MSB N – 15 D08 N – 15 D07 N – 15 D06 N – 15 D05 N – 16 |
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