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ADIS16488A Datasheet(PDF) 31 Page - Analog Devices |
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ADIS16488A Datasheet(HTML) 31 Page - Analog Devices |
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31 / 35 page  Product Overview Online Documentation Design Resources Discussion Sample & Buy Data Sheet ADIS16488A Rev. C | Page 31 of 35 Table 118. FNCTIO_CTRL (Page 3, Base Address = 0x06) Bits Description (Default = 0x000D) [15:12] Not used 11 Alarm indicator: 1 = enabled, 0 = disabled 10 Alarm indicator polarity: 1 = positive, 0 = negative [9:8] Alarm indicator line selection: 00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4 7 Sync clock input enable: 1 = enabled, 0 = disabled 6 Sync clock input polarity: 1 = rising edge, 0 = falling edge [5:4] Sync clock input line selection: 00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4 3 Data-ready enable: 1 = enabled, 0 = disabled 2 Data ready polarity: 1 = positive, 0 = negative [1:0] Data ready line selection: 00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4 Data-Ready Indicator FNCTIO_CTRL[3:0]providesomeconfiguration options for using one of the DIOx lines as a data ready indicator signal, which can drivetheinterruptcontrol line of a processor. The factory default assigns DIO2 as a positive polarity, data ready signal. Use the following sequence to changethis assignment to DIO1 with a negative polarity: turn to Page 3 (DIN = 0x8003) and set FNCTIO_CTRL[3:0]= 1000 (DIN= 0x8608, thenDIN= 0x8700). The timing jitter on the data ready signal is ±1.4 µs. Input Sync/Clock Control FNCTIO_CTRL[7:4]providesomeconfiguration options for using one of the DIOx lines as an input synchronization signal for sampling inertial sensor data. For example, use the following sequencetoestablishDIO4 asa positivepolarity, input clockpin and keepthefactory defaultsetting for thedataready function: turn to Page 3 (DIN = 0x8003) and set FNCTIO_CTRL[7:0]= 0xFD (DIN = 0x86FD, then DIN = 0x8700). Note that this command also disables the internal sampling clock, and no data sampling occurs without the input clocksignal. When selecting a clock input frequency, consider the 330 Hzsensor bandwidth becauseundersampling the sensors can degrade noise and stability performance. General-Purpose Input/Output Control When FNCTIO_CTRL doesnot configure a DIOx pin, GPIO_CTRL providesregister controls forgeneral-purposeuse of the pin. GPIO_CTRL[3:0]provides input/output assignment controls for each line. When the DIOx lines areinputs, monitor their level by reading GPIO_CTRL[7:4]. When the DIOx lines are used asoutputs, settheir level bywriting toGPIO_CTRL[7:4]. For example, use the following sequence to set DIO1 and DIO3 as high and low outputlines, respectively,andset DIO2 and DIO4 asinputlines. Turnto Page3 (DIN = 0x8003)and set GPIO_CTRL[7:0]= 0x15 (DIN = 0x8815, then DIN = 0x8900). Table 119. GPIO_CTRL (Page 3, Base Address = 0x08) Bits Description (Default = 0x00X0)1 [15:8] Don’t care 7 General-Purpose input/output Line 4 (DIO4) data level 6 General-Purpose input/output Line 3 (DIO3) data level 5 General-Purpose input/output Line 2 (DIO2) data level 4 General-Purpose input/output Line 1 (DIO1) data level 3 General-Purpose input/output Line 4 (DIO4) direction control (1 = output, 0 = input) 2 General-Purpose input/output Line 3 (DIO3) direction control (1 = output, 0 = input) 1 General-Purpose input/output Line 2 (DIO2) direction control (1 = output, 0 = input) 0 General-Purpose input/output Line 1 (DIO1) direction control (1 = output, 0 = input) 1 The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting. POWER MANAGEMENT The SLP_CNT register(see Table 120)provides controls for both power-down mode andsleepmodes.Thetrade-off between power-downmodeand sleepmodeis between idle powerand recovery time. Power-down mode offers the best idle power consumption but requires themost timeto recover. In addition, all volatilesettings arelostduring power-down but arepreserved during sleep mode. For timed sleepmode,turn toPage 3 (DIN=0x8003), writethe amount of sleeptimetoSLP_CNT[7:0]andthen,setSLP_CNT[8] = 1 (DIN = 0x9101)to start thesleepperiod. For a timed power-down period,changethelastcommand toset SLP_CNT[9]= 1 (DIN= 0x9102). To power down or sleep for an indefinite period, set SLP_CNT[7:0]= 0x00 first, then set either SLP_CNT[8]or SLP_CNT[9]to 1. Note that the command takes effect when the CS line goeshigh. To awaken thedevice fromsleeporpower-downmode, use oneof the following options to restore normal operation: • Assert CS from high to low. • Pulse RST low, then high again. • Cycle the power. For example, set SLP_CNT[7:0]= 0x64 (DIN = 0x9064), then set SLP_CNT[8]= 1 (DIN = 0x9101) to start a sleep period of 100 seconds. If the sleep mode and power-down mode bits are both set high, the normal sleep modebit (SLP_CNT[8])takes precedence. Table 120. SLP_CNT (Page3, Base Address = 0x10) Bits Description [15:10] Not used 9 Power-down mode 8 Normal sleep mode [7:0] Programmable time bits; 1 sec/LSB; 0x00 = indefinite |
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