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ADIS16485 Datasheet(PDF) 6 Page - Analog Devices |
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ADIS16485 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 32 page  ADIS16485 Data Sheet TIMING SPECIFICATIONS TA = 25°C, VDD = 3.3 V, unless otherwise noted. Table 2. Normal Mode Parameter Description Min1 Typ Max1 Unit fSCLK Serial clock 0.01 15 MHz tSTALL2 Stall period between data communication cycles 2 µs tCLS Serial clock low period 31 ns tCHS Serial clock high period 31 ns t CS Chip select to clock edge 32 ns tDAV DOUT valid after SCLK edge 10 ns tDSU DIN setup time before SCLK rising edge 2 ns tDHD DIN hold time after SCLK rising edge 2 ns tDR, tDF DOUT rise/fall times, ≤100 pF loading 3 8 ns tDSOE CS assertion to data out active 0 11 ns tHD SCLK edge to data out invalid 0 ns tSFS Last SCLK edge to CS deassertion 32 ns tDSHI CS deassertion to data out high impedance 0 9 ns t1 Input sync pulse width 5 µs t2 Input sync to data invalid 510 µs t3 Input sync period 417 µs 1 Guaranteed by design and characterization, but not tested in production. 2 See Table 3 for exceptions to the stall time rating. Table 3. Register Specific Stall Times Register Function Minimum Stall Time (μs) FNCTIO_CTRL Configure DIOx functions 60 FLTR_BNK0 Enable/select FIR filter banks 320 FLTR_BNK1 Enable/select FIR filter banks 320 NULL_CFG Configure autonull bias function 10 GLOB_CMD[1] Self test 12000 GLOB_CMD[2] Memory test 50000 GLOB_CMD[3] Flash memory update 375000 GLOB_CMD[6] Flash memory test 75000 GLOB_CMD[7] Software reset 12000 Timing Diagrams CS SCLK DOUT DIN 1 2 3 4 5 6 15 16 R/W A5 A6 A4 A3 A2 D2 MSB DB14 D1 LSB DB13 DB12 DB10 DB11 DB2 LSB DB1 tCS tDSHI tDR tSFS tDF tDAV tHD tCHS tCLS tDSOE tDHD tDSU Figure 2. SPI Timing and Sequence Rev. E | Page 6 of 32 |
Similar Part No. - ADIS16485_15 |
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Similar Description - ADIS16485_15 |
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