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CLC021 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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CLC021 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 18 page  Timing Diagram Device Operation The CLC021 SMPTE 259M Serial Digital Video Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts parallel component or composite digi- tal video signals into serial format. Logic levels within this equipment are normally TTL-compatible as produced by CMOS or bipolar logic devices. The encoder produces ECL- compatible serial digital video (SDV) signals conforming to SMPTE 259M-1997. The CLC021 operates at all standard SMPTE and ITU-R parallel data rates. In addition, the CLC021 can serialize other 8- and 10-bit data. VIDEO DATA PROCESSING CIRCUITS The input data register accepts 8- or 10-bit parallel data and clock signals having HCMOS/LSTTL-compatible signal levels. Parallel data may conform to any of several stan- dards: SMPTE 125M, SMPTE 267M, SMPTE 244M or ITU-R BT.601. If the data is 8-bit, it is converted to a 10-bit representation according to the type of data being input: component 4:2:2 per SMPTE 259M paragraph 7.1.1, com- posite NTSC per paragraph 8.1.1 or composite PAL per paragraph 9.1.1. Eight-bit video data corresponds to the upper 8 bits of the 10-bit video data word and is MSB- aligned. Output from this register feeds the TRS (sync) character detector, SMPTE polynomial generator/serializer and the EDH polynomial generators/serializers and control system. All parallel data and clock inputs have internal pull- down devices. The sync detector or TRS character detector receives data from the input register. The detection function is controlled by Sync Detect Enable, a low-true, TTL-compatible, external signal. Synchronization words, the timing reference signals (TRS), start-of-active-video (SAV) and end-of-active-video (EAV) are defined in SMPTE 125M and 244M. The sync detector supplies control signals to the SMPTE polynomial generator to identify the presence of valid video data, and to the EDH control block. In SMPTE mode, TRS character LSB-clipping as prescribed in ITU-R BT.601 is enabled. LSB- clipping causes all TRS characters with a value between 000h and 003h to be forced to 000h and all TRS characters with a value between 3FCh and 3FFh to be forced to 3FFh. Clipping is done prior to encoding or EDH character genera- tion. This function is disabled in non-SMPTE mode opera- tion. Outputs from the sync detector are: 1. H, V, and F or Line/Field ID — For component video, these are registered outputs corresponding to input TRS data bits 6, 7 and 8, respectively. These outputs are disabled in non-SMPTE mode. The outputs are active HIGH-true. For composite video, these outputs corre- spond to the line and field ID encoded as input parallel data bits 2 (MSB) through 0. These outputs are regis- tered for the duration of the applicable field. 2. NSP — New Sync Position: A function and output indi- cating that a new or out-of-place TRS character has been detected. This output remains active for at least one horizontal line period (reset by EAV) or unless re- activated by a subsequent new or out-of-place TRS. Activation of this function flushes the existing state of the machine reseting the EDH generator, SMPTE polyno- mial generator, serializer and NRZ-NRZI converter. This function is disabled in non-SMPTE mode operation. The output is active HIGH-true. 3. ANC — Ancilliary data location output: Indicates that the ancilliary data header (component) or flag (composite) has been detected. The output is a pulse having a duration of one P CLK period. The output is active HIGH- true. SMPTE POLYNOMIAL GENERATOR AND CONTROLS The SMPTE Mode input allows the CLC021 to function both as a full SMPTE 259M encoder or general-purpose 8- or 10-bit serializer. SMPTE mode is enabled when this input is LOW. Non-SMPTE mode is enabled when this pin is HIGH. This pin is pulled internally to V SS when unconnected. When in SMPTE mode, the SMPTE polynomial generator; TRS sync detection circuitry; EDH control circuitry; H, V, F and NSP outputs and TRS clipping are enabled. The SMPTE polynomial generator accepts the parallel video data and encodes it using the polynomial X 9 +X4 +1 as specified in SMPTE 259M (1997 rev.), paragraph 5 and Annex C. The transmission bit order is LSB-first, per para- graph 6. 10136805 FIGURE 3. Setup and Hold Timing www.national.com 8 |
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