Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

10

Cm = MASTER BUS

CAPACITANCE

Cb = BUFFERED BUS

WIRING CAPACITANCE

Cs = SLAVE BUS

CAPACITANCE

MASTER

SLAVE

P82B96

P82B96

SDA

Rm

Rb

Rs

SDA

Sx

Tx/Rx

Tx/Rx

Sx

GND/0 V

C)

RISING EDGE OF SDA AT SLAVE IS DELAYED BY THE BUFFERS AND BUS RISE TIMES

EFFECTIVE DELAY OF SDA AT MASTER = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) (ns),

C = F,

R =

Ω

LOCAL MASTER BUS

BUFFERED EXPANSION BUS

REMOTE SLAVE BUS

su01789

Figure 8.

Figures 6, 7, and 8 show the P82B96 used to drive extended bus

wiring, with relatively large capacitance, linking two Fast mode

relevant timing calculations for 3.3/5 V operation. Because the

buffers and the wiring introduce timing delays, it may be necessary

to decrease the nominal SCL frequency below 400 kHz. In most

cases the actual bus frequency will be lower than the nominal

Master timing due to bit-wise stretching of the clock periods.

The delay factors involved in calculation of the allowed bus speed

are:

A) The propagation delay of the Master signal through the buffers

and wiring to the Slave. The important delay is that of the falling

edge of SCL because this edge ‘requests’ the data or

Acknowledge from a Slave.

B) The effective stretching of the nominal LOW period of SCL at the

Master caused by the buffer and bus rise times

C) The propagation delay of the Slave’s response signal through the

buffers and wiring back to the Master. The important delay is

that of a rising edge in the SDA signal. Rising edges are always

slower and are therefore delayed by a longer time than falling

edges. (The rising edges are limited by the passive pull-up while

falling edges are actively driven)

response (which is provided in response to a falling edge of SCL)

must be received at the Master before the end of the corresponding

low period of SCL as appears on the bus wiring at the Master. Since

all Slaves will, as a minimum, satisfy the worst case timing

requirements of a 400 kHz part, they must provide their response

within the minimum allowed clock LOW period of 1300 ns. Therefore

in systems that introduce additional delays it is only necessary to

extend that minimum clock low period by any “effective” delay of the

Slave’s response. The effective delay of the slaves response = total

delays in SCL falling edge from the Master reaching the Slave (A) –

the effective delay (stretch) of the SCL rising edge (B) + total delays

in the Slave’s response data, carried on SDA, reaching the

Master (C).

The Master microcontroller should be programmed to produce a

nominal SCL LOW period = (1300 + A – B + C) ns, and should be

programmed to produce the nominal minimum SCL HIGH period of

600 ns. Then a check should be made to ensure the cycle time is

not shorter than the minimum 2500 ns. If found necessary, just

increase either clock period.

Due to clock stretching, the SCL cycle time will always be longer

than (600 + 1300 + A + C) ns.

Example:

The buffered bus has a capacitance of 1 nF and a pull-up resistor of

160 ohms to 5 V giving an RbCb product of 160 ns. The Slave bus

also has an RsCs product of 100 ns.

The microcontroller LOW period should be programmed to

≥ (1300 + 372.5 – 482 + 472) ns, that is ≥ 1662.5 ns.

Its HIGH period may be programmed to the minimum 600 ns.

The nominal microcontroller clock period will be

≥ (1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of

442 kHz.

The actual bus clock period, including the 482 ns clock stretch

effect, will be below (nominal + stretch) = (2262.5 + 482) ns or

≥ 2745 ns, equivalent to an allowable frequency of 364 kHz.