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TLP550 Datasheet(PDF) 4 Page - Toshiba Semiconductor |
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TLP550 Datasheet(HTML) 4 Page - Toshiba Semiconductor |
4 / 7 page TLP550 2002-09-25 4 (Note 6) Device considered two -terminal device: Pins 1, 2, 3 and 4 shorted together and pin 5, 6, 7 and 8 shorted together. (Note 7) Switching time test circuit. (Note 8) Common mode transient immunity test circuit. (Note 9) Maximum electrostatic discharge voltage for any pins: 100V (C = 200pF, R = 0) VCC=5V VO Pulse input Output monitor RL 6 4 3 1 5 7 PW = 100µs Duty ratio = 1 / 10 IF monitor IF 8 2 IF VO 0 5V 1.5V VOL 1.5V tpHL tpLH VCM 200V VO (IF = 0mA) VO (IF = 16mA) 0V 5V 2V 0.8V VOL 10% 90% tf tr VCC=5V VO Output monitor RL 6 4 3 1 5 7 IF 8 2 VCM Pulse gen ZO=50Ω CMH= CML= 160 (V) 160 (V) , tf (µs) tf (µs) |
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