Introduction

Encapsulated power semiconductors in packages

such as the TO-220 or D-Pak are fairly easy to model

thermally, using only one thermal parameter. The

assumption is that most of the power generated in the

silicon chip travels in one direction. The assumption is

reasonable because the silicon chip is soldered (or

epoxy-attached) to a lead frame that provides the

main cooling path to the environment. Heat flow in the

opposite direction is limited because the die is

insulated with a layer of encapsulation ‘plastic’. The

dissipation of heat from the lead-frame into the

environment is often enhanced by fitting a heat sink.

DirectFET

encourages heat to disperse from the die in opposite

directions, cooling through both the substrate pad

connections (source and gate) and the metal can on

top of the device. The can-to-ambient thermal

interface can be maximized by fitting a heat sink. The

design of the can also provides a parallel or shunt

thermal path from the can to substrate.

Figure 1 shows the direction of heat flow from a

DirectFET device and an approximate thermal

equivalent circuit for such a device in use.

Measuring the thermal resistance of a DirectFET

device inevitably produces a composite result based

on the temperatures measured at the junction, can or

substrate using the total power dissipated by the

silicon. While this gives the effective thermal

resistance under particular cooling conditions, it does

not give a value that applies under other conditions.

When determining a value for dual-sided cooling

conditions, the most significant factors are the thermal

resistance of the heat sink and substrate. To assess

these correctly, the power flow through each path

must be known. This requires a method of predicting

the proportion of power flow through the paths. The

temperature of the can and the substrate will change

with different levels of can and substrate cooling.

Indeed, it is this feature of DirectFET construction –

which enables cooling from both sides of the silicon

die – that gives the devices their particular benefits.

This application note provides an easy method for

assessing the proportion of power flow from each of a

DirectFET device’s surfaces, so that the appropriate

thermal resistance figures are used and the true rating

is accurately determined.

can heat sink

junction

substrate

heat sink

interface material

can (drain)

source pads

gate pad

Tambient

Rth chassis / heat sink

T chassis / heat sink

Rth gap filler

Tcan

Rth can-substrate

(can)

Rth junction-can

Tjunction

Rth junction-substrate

(source)

Tsubstrate

Rth substrate

Rth heat sink

(substrate attachment,

if present)

Tambient

Figure 1a Directions of heat flow (indicated by the red arrows)

Figure 1b Approximate thermal equivalent circuit

DirectFET

AN-1059

Thermal Model and Rating Calculator

www.irf.com

Version 3, September 2010

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