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AN-944 Datasheet(PDF) 4 Page - International Rectifier

Part # AN-944
Description  Application Note
Download  5 Pages
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

AN-944 Datasheet(HTML) 4 Page - International Rectifier

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AN-944 (v.Int)
Figure 4. Basic Gate Charge Test Circuit
The required gate drive current is derived by simply dividing the gate charge, 15 X 10
-9, by the required switching time, 100 X
10
-9, giving 150 mA. From this calculation, the designer can further arrive at the drive circuit impedance. If the drive circuit
applies 14 volts to the gate, for instance, then a drive impedance of about 50 ohms would be required. Note that throughout the
“flat” part of the switching period (Figure 3), the gate voltage is constant at about 7 volts. The difference between the applied 14
volts and 7 volts is what is available to drive the required current through the drive circuit resistance.
The gate charge data also lets the designer quickly determine average gate drive power. The average gate drive power, PDRIVE, is
QGVGf. Taking the above 100 kHz switcher as an example, and assuming a gate drive voltage VG of 14 volts, the appropriate
value of gate charge QG is 27 nanocoulombs (point C on Figure 3). The average drive power is therefore 27 X 10
-9 X 14 X 105 =
0.038 Watts. Even though the 150 mA drive current which flows during the switching interval may appear to be relatively high.
the average power is minuscule (0.004%) in relation to the power being switched in the drain current. This is because the drive
current flows for such a short period that the average power is negligible. Thus actual drive power for MOSFETs is minute
compared to bipolar requirements, which must sustain switching current during the entire ON condition. Average drive power, of
course, increases at higher frequencies, but even at 5 MHz it would be only 1.9W.
3.
The Gate Charge Curve
The oscillograms of the gate-to-source voltage in Figure 2 neatly delineate between the charge required for the gate-to-source
capacitance, and the charge required for the gate-to-drain, or “Miller” capacitance. The accompanying simplified test circuit and
waveform diagram ( Figures 4 and 5 respectively) give the explanation. Before time t0, the switch S is closed; the device under
test (DUT) supports the full circuit voltage, VDD, and the gate voltage and drain current are zero. S is opened at time t0; the gate-
to-source capacitance starts to charge, and the gate-to-source voltage increases. No current flows in the drain until the gate
reaches the threshold voltage. During period T1 to t2, the gate-to-source capacitance continues to charge, the gate voltage
continues to rise and the drain current rises proportionally. So long as the actual drain current is still building up towards the
available drain current, ID, the freewheeling rectifier stays in conduction, the voltage across it remains low, and the voltage across
the DUT continues to be virtually the full circuit voltage, VDD. The top end of the drain-to-gate capacitance CAD therefore
remains at a fixed potential, whilst the potential of the lower end moves with that of the gate. The charging current taken by CAD
during this period is small, and for practical purposes it can be neglected, since CAD is numerically small by comparison with
GCS.
At time t2, the drain current reaches ID, and the freewheeling rectifier
shuts off; the potential of the drain now is no longer tied to the supply
voltage, VDD. The drain current now stays constant at the value ID
enforced by the circuit, whilst the drain voltage starts to fall. Since the
gate voltage is inextricably related to the drain current by the intrinsic
transfer characteristic of the DUT (so long as operation remains in the
“active” region), the gate voltage now stays constant because the
“enforced” drain current is constant. For the time being therefore, no
further charge is consumed by the gate-to-source capacitance, because
the gate voltage remains constant. Thus the drive current now diverts,
in its entirety, into the “Miller” capacitance CAD, and the drive circuit
charge now contributes exclusively to discharging the “Miller”
capacitance.
The drain voltage excursion during the period t2 to t3 is relatively large,
and hence the total drive charge is typically higher for the “Miller”
capacitance CAD than for the gate-to-source capacitance GCS. At t3 the
drain voltage falls to a value equal to ID x RDS(ON) , and the DUT now
comes out of the “active” region of operation. (In bipolar transistor
terms, it has reached “saturation.”
The gate voltage is now no longer constrained by the transfer characteristic of the device to relate to the drain current, and is free
to increase. This it does, until time t4, when the gate voltage becomes equal to the voltage “behind” the gate circuit current
source. The time scale on the oscillogram of the gate-to-source voltage is directly proportional to the charge delivered by the
drive circuit, because charge is equal to the product of current and time, and the current remains constant throughout the whole
sequence. Thus the length of the period t0 to t1 represents the charge QGS consumed by the gate-to-source capacitance, whilst the
length of the period t2 to t3 represents the charge QGD consumed by the gate-to-drain or "Miller" capacitance. The total charge at
time t3 is the charge required to switch the given voltage VDD and current ID. The additional charge consumed after time t3 does
not represent “switching” charge; it is simply the excess charge which will be delivered by the drive circuit because the amplitude
of the applied gate drive voltage normally will be higher (as a matter of good design practice) than the bare minimum required to
accomplish switching.
I
G
S
C
GS
S
G
C
DG
D
I
D
+V
DD


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