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CLC416AJ Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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CLC416AJ Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 6 page  Figure 3: Input Referred Crosstalk vs. Frequency Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC416 will improve stability. The Rs vs. Capacitive Load plot, in the Typical Performance section, gives the recommended series resistance value for optimum flatness at various capacitive loads. Power Dissipation The power dissipation of an amplifier can be described in two conditions: s Quiescent Power Dissipation - PQ (No Load Condition) s Total Power Dissipation - PT (with Load Condition) The following steps can be taken to determine the power consumption for each CLC416 amplifier: 1. Determine the quiescent power PQ = Icc (VCC -VEE) 2. Determine the RMS power at the output stage PO = (Vcc - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Determine the total RMS power PT = PQ + PO Add the total RMS powers for both channels to deter- mine the power dissipated by the dual. The maximum power that the package can dissipate at a given temperature is illustrated in the Power Derating curves in the Typical Performance section. The power derating curve for any package can be derived by utilizing the following equation: where: Tamb = Ambient temperature (°C) θ JA = Thermal resistance, from junction to ambient, for a given package (°C/W) Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC416 (CLC730038 - DIP, CLC730036 - SOIC) and suggests their use as a guide for high frequency layout and as an aid for device test- ing and characterization. Supply bypassing is required for best performance. The bypass capacitors provide a low impedance return current path at the supply pins. They also provide high frequency filtering on the power supply traces. Other layout factors play a major role in high frequency performance. The following are recommended as a basis for high frequency layout: 1. Include 6.8 µF tantalum and 0.1µF ceramic capacitors on both supplies. 2. Place the 6.8 µF capacitors within 0.75 inches of the power pins. 3. Place the 0.1 µF capacitors within 0.1 inches of the power pins. 4. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. 5. Minimize all trace lengths to reduce series inductances. Additional information is included in the evaluation board literature. SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: s Support Berkeley SPICE 2G and its many derivatives s Reproduce typical DC, AC, Transient, and Noise performance s Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled para- meters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. Applications Circuits Instrumentation Amplifier An instrumentation circuit is shown on the front page and reproduced in Figure 4. The DC CMRR can be fine tuned by adjusting R1. Figure 4: Instrumentation Amplifier P (175 Tamb) JA = °− θ + - 348 Ω 1/2 CLC416 R1 348 Ω - + 1/2 CLC416 348 Ω 348 Ω Vout = 3(V2 - V1) 348 Ω 348 Ω 348 Ω - + CLC405 V1 V2 Frequency (MHz) -120 -100 -80 -60 -40 -20 1 100 10 5 http://www.national.com |
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