A43L3616V-7 datasheet(3/41 Pages) AMICC

Part #	A43L3616V-7

Description	2M X 16 Bit X 4 Banks Synchronous DRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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A43L3616

(February, 2002, Version 3.0)

3

AMIC Technology, Inc.

Pin Descriptions

Symbol

Name

Description

CLK

System Clock

Active on the positive going edge to sample all inputs.

CS

Chip Select

Disables or Enables device operation by masking or enabling all inputs except

CLK, CKE and L(U)DQM

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one clock + tss prior to new command.

Disable input buffers for power down in standby.

A0~A11

Address

Row / Column addresses are multiplexed on the same pins.

Row address : RA0~RA11, Column address: CA0~CA8

BS0, BS1

Bank Select Address

Selects bank to be activated during row address latch time.

Selects band for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS

Column Address

Strobe

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE

Write Enable

Enables write operation and Row precharge.

L(U)DQM

Data Input/Output

Mask

Makes data output Hi-Z, t SHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQ0-15

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power

Supply/Ground

Power Supply: +3.3V

±0.3V/Ground

VDDQ/VSSQ

Data Output

Power/Ground

Provide isolated Power/Ground to DQs for improved noise immunity.

NC/RFU

No Connection

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