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FM25V02A Datasheet(PDF) 8 Page - Cypress Semiconductor |
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FM25V02A Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 23 page  FM25V02A Document Number: 001-90865 Rev. *F Page 8 of 23 Memory Operation The SPI interface, which is capable of a high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike serial flash and EEPROMs, the FM25V02A can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory begin with a WREN opcode with CS being asserted and deasserted. The next opcode is WRITE. The WRITE opcode is followed by a two-byte address containing the 15-bit address (A14-A0) of the first data byte to be written into the memory. The upper bit of the two-byte address is ignored. Subsequent bytes are data bytes, which are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and keeps CS LOW. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. The rising edge of CS terminates a write operation. A write operation is shown in Figure 11. Note When a burst write reaches a protected block address, the automatic address increment stops and all the subsequent data bytes received for write will be ignored by the device. EEPROMs use page buffers to increase their write throughput. This compensates for the technology's inherently slow write operations. F-RAM memories do not have page buffers because each byte is written to the F-RAM array immediately after it is clocked in (after the eighth clock). This allows any number of bytes to be written without page buffer delays. Note If the power is lost in the middle of the write operation, only the last completed byte will be written. Read Operation After the falling edge of CS, the bus master can issue a READ opcode. Following the READ command is a two-byte address containing the 15-bit address (A14-A0) of the first byte of the read operation. The upper bit of the address is ignored. After the opcode and address are issued, the device drives out the read data on the next eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes, which are read out sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and CS is LOW. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of CS terminates a read operation and tristates the SO pin. A read operation is shown in Figure 12. Fast Read Operation The FM25V02A supports a FAST READ opcode (0Bh) that is provided for code compatibility with serial flash devices. The FAST READ opcode is followed by a two-byte address containing the 15-bit address (A14-A0) of the first byte of the read operation and then a dummy byte. The dummy byte inserts a read latency of an 8-clock cycle. The fast read operation is otherwise the same as an ordinary read operation except that it Figure 9. RDSR Bus Configuration Figure 10. WRSR Bus Configuration (WREN not shown) CS SCK SO 01234567 SI 00 0 0 0 1 0 0 1 HI-Z 0 12345 6 7 LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 Opcode Data CS SCK SO 0 1 2 3 4567 SI 00 00 0 0 0 1 MSB LSB D2 D3 D7 HI-Z 0 12345 67 Opcode Data X X X X X |
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