Document Number: 001-97964 Rev. *E

Page 6 of 29

S27KL0641, S27KS0641

ADVANCE

3.2

Read Transactions

Note:

1. The Latency Code is the value loaded into Configuration Register bits CR0[7:4].

3.3

Write to Memory Space Transactions

When a linear burst write reaches the last address in the array, continuing the burst beyond the last address has undefined results.

15-3

Reserved

Reserved for future column address expansion.

Reserved bits should be set to 0 by the HyperBus master.

2-0

Lower Column

(word) Address

Lower Column component of the target address: System word address bits A2-0 selecting the

starting word within a row.

Table 3.2 Maximum Operating Frequency For Latency Code Options

Latency Code

Latency Clocks

Maximum Operating Frequency

(MHz)

0000

5

133

0001

6

166

0010

Reserved

NA

0011

Reserved

NA

0100

Reserved

NA

0101

Reserved

NA

0110

Reserved

NA

0111

Reserved

NA

1000

Reserved

NA

1001

Reserved

NA

1010

Reserved

NA

1011

Reserved

NA

1100

Reserved

NA

1101

Reserved

NA

1110

3

83

1111

4

100

Table 3.1 Command-Address Bit Definitions (Continued)

CA Bit#

Bit Name

Bit Function