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CLC5506PCASM Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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CLC5506PCASM Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 12 page Electrical Characteristics (Continued) These conditions apply unless otherwise specified: T J = 25˚C, VCCA = VCCD = +5V: Gain = 25.75dB, RLdiff = 100Ω, Pin = −30dBm (Note 6),(Note 7). Symbol Parameter Conditions Typ (Note 3) Limit (Note 4) Units Input/Output Characteristics: output resistance Differential 5K Ω output capacitance Differential 0.5 pF Logic I/O clock speed Maximum 1 MHz data to clock setup time, T CS Minimum 50 nsec data to clock hold time, T CH Minimum 10 nsec clock pulse width high, T CWH Minimum 50 nsec clock pulse width low, T CWL Minimum 50 nsec clock to load enable setup time, T ES Minimum 50 nsec high level input voltage 0.7 V CCD V low level input voltage 0.3 V CCD V High level input current ±1.0 µA low level input current ±1.0 µA high level output voltage Isource = 0.5mA V CCD −0.8 V low level output voltage Isink = 0.5mA 0.4 V DC Characteristics: Supply current 75 95 mA Supply current in power down mode 35 100 µA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in- tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: Human body model, 1.5k Ω in series with 100pF. Machine model, 200Ω in series with 100pF. Note 3: Typical values represent the most likely parametric norm. Note 4: All limits are guaranteed by testing or statistical analysis, unless otherwise noted. Note 5: AC test performed at 400MHz unless otherwise noted. Note 6: Refer to test circuit schematic, loss of transformers is excluded from the measurement. Note 7: Refer to test circuit schematic to see the definition of RLdiff. www.national.com 5 |
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