 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CLC5523IN Datasheet(PDF) 6 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
CLC5523IN Datasheet(HTML) 6 Page - National Semiconductor (TI) |
|
|
6 / 12 page  http://www.national.com 6 The CLC425 is a low noise wideband voltage feedback amplifier. Setting R2 at 909 W and R1 at 100W produces a gain of 20dB. Setting Rf at 1000W as recommended and Rg at 50W, produces a gain of 26dB in the CLC5523. The total gain of this circuit is therefore approximately 46dB. It is important to understand that when partitioning to obtain high levels of gain, very small signal levels will drive the amplifiers to full scale output. For example, with 46dB of gain, a 20mV signal at the input will drive the out- put of the CLC425 to 200mV, the output of the CLC5523 to 4V. Accordingly, the designer must carefully consider the contributions of each stage to the overall characteris- tics. Through gain partitioning the designer is provided with an opportunity to optimize the frequency response, noise, distortion, settling time, and loading effects of each amplifier to achieve improved overall performance. CLC5523 Gain Control Range and Minimum Gain Before discussing Gain Control Range, it is important to understand the issues which limit it. The minimum gain of the CLC5523, theoretically, is zero, but in practical circuits is limited by the amount of feedthrough, here defined as the difference in output levels when VG = 2V and when VG = 0V. Capacitive coupling through the board and package as well as coupling through the supplies will determine the amount of feedthrough. Even at DC, the input signal will not be completely rejected. At high fre- quencies feedthrough will get worse because of its capac- itive nature. At low frequencies, the feedthrough will be 80dB below the maximum gain, and therefore it can be said that the CLC5523 has an 80dB Gain Control Range. CLC5523 Gain Control Function In the two plots, Gain vs. VG, we can see the gain as a function of the control voltage. The first plot, sometimes referred to as the S-curve, is the linear (V/V ) gain. This is a hyperbolic tangent relationship. The second gain curve plots the gain in dB and is linear over a wide range of gains. Because of this, the CLC5523 gain control is referred to as “linear-in-dB.” For applications where the CLC5523 will be used at the heart of a closed loop AGC circuit, the S-curve control characteristic provides a broad linear (in dB) control range with soft limiting at the highest gains where large changes in control voltage result in small changes in gain. For applications, requiring a fully linear (in dB) control characteristic, use the CLC5523 at half gain and below (VG ² 1V). Avoiding Overdrive of the CLC5523 Gain Control Input There is an additional requirement for the CLC5523 Gain Control Input (VG): VG must not exceed +2.5V. The gain control circuitry may saturate and the gain may actually be reduced. In applications where VG is being driven from a DAC, this can easily be addressed in the software. If there is a linear loop driving VG, such as an AGC loop, other methods of limiting the input voltage should be implemented. One simple solution is to place a 2:1 resistive divider on the VG input. If the device driving this divider is operating off of ±5V supplies as well, its output will not exceed 5V and through the divider VG can not exceed 2.5V. Improving the CLC5523 Large Signal Performance Figure 2 illustrates an inverting gain scheme for the CLC5523. Figure 2: Inverting the CLC5523 The input signal is applied through the Rg resistor. The Vin pin should be grounded through a 25W resistor. The maximum gain range of this configuration is given in the following equation: The inverting slew rate of the CLC5523 is much higher than that of the non-inverting slew rate. This 2.5X performance improvement comes about because in the non-inverting configuration, the slew rate of the overall amplifier is limited by the input buffer. In the inverting circuit, the input buffer remains at a fixed voltage and does not affect slew rate. Transmission Line Matching One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor at the input or output of the amplifier. Figure 3 shows a typ- ical circuit configuration for matching transmission lines. Figure 3: Transmission Line Matching The resistors Rs, Ri, Ro, and RT are equal to the characteristic impedance, Zo, of the transmission line or cable. Use Co to match the output transmission line over a greater frequency range. It compensates for the increase of the op amp’s output impedance with frequency. CLC5523 Rf Vin 2 3 4 1 VG 6 7 25 W 25 W Rg Vo A R R vmax f g =- æ è ç ö ø ÷ CLC5523 Rf 2 3 4 1 VG 6 7 25 W Rg Co Zo RT Output Ro Zo Signal Input + - Ri Rs |
Similar Part No. - CLC5523IN |
|
Similar Description - CLC5523IN |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
