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DM632B Datasheet(PDF) 6 Page - Silicon Touch Technology Inc. |
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DM632B Datasheet(HTML) 6 Page - Silicon Touch Technology Inc. |
6 / 31 page 點晶科技股份有限公司 SILICON TOUCH TECHNOLOGY INC . 新竹市科學園區展業一路9號7樓之1 9-7F-1, Prosperity RoadⅠ, Hsin-Chu, Taiwan, R.O.C. Tel:886-3-5645656 Fax:886-3-5645626 16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 5 未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. DM632B Maximum Ratings (Ta=25°C, Tj(max) = 150°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage VCC -0.3 ~ 7.0 V Input Voltage VIN -0.3 ~ VCC+0.3 V Output Current IOUT 70 mA Output Voltage VOUT -0.3 ~ 17 V Input Clock Frequency FDCK 25 MHz GND Terminal Current IGND 1120 mA 4.17 ( TSSOP24E exposed pad) 2.19 ( SOP24B) 1.87 (DIP24B) Power Dissipation (4 layer PCB, at Ta=25℃) PD 1.79 ( SSOP24 ) W 30 ( TSSOP24E exposed pad) 57 (SOP24B) 67 (DIP24B) Thermal Resistance (4 layer PCB, at Ta=25℃) Rth(j-a) 70 (SSOP24 ) °C/W Operating Temperature Top -40 ~ 85 °C Storage Temperature Tstg -55 ~ 150 °C Recommended Operating Condition CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT Supply Voltage VCC ⎯ 3.3 5.0 5.5 V Output Voltage VOUT Driver On *1 1.0 ⎯ 0.5VCC Output Voltage VOUT Driver Off *2 ⎯ ⎯ 17 V IO OUTn 5 ⎯ 60 IOH VOH = VCC – 0.4 V ⎯ ⎯ +1.5 Output Current IOL VOL = 0.2 V ⎯ ⎯ - 1.5 mA VIH 0.8VCC ⎯ VCC Input Voltage VIL VCC = 3.3 V ~ 5.5V 0.0 ⎯ 0.2VCC V Input Clock Frequency FDCK Single Chip Operation ⎯ ⎯ 25 Input PWM Frequency FGCK 3.3V~5.5V ⎯ ⎯ 25 MHz LAT Pulse Width tw LAT 15 ⎯ ⎯ DCK Pulse Width tw DCK 15 ⎯ ⎯ Set-up Time for DAI tsetup(D) 10 ⎯ ⎯ Hold Time for DAI thold(D) 10 ⎯ ⎯ Set-up Time for LAT tsetup(L) 10 ⎯ ⎯ Hold Time for LAT thold(L) VCC = 5.0V 360 *3 ⎯ ⎯ ns *1 Notice that the power dissipation is limited to its package and ambient temperature. *2 The driver output voltage including any overshoot stress has to be compliant with the maximum voltage (17V). *3 Due to open detection operation and output channel delay consideration. |
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