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NCP1200D100R2G Datasheet(PDF) 8 Page - ON Semiconductor |
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NCP1200D100R2G Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 16 page NCP1200 www.onsemi.com 8 3. Permanently force the VCC level above VCCH with an auxiliary winding. It will automatically disconnect the internal startup source and the IC will be fully self−supplied from this winding. Again, the total power drawn from the mains will significantly decrease. Make sure the auxiliary voltage never exceeds the 16 V limit. Skipping Cycle Mode The NCP1200 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 18 ). Suppose we have the following component values: Lp, primary inductance = 1 mH FSW, switching frequency = 48 kHz Ip skip = 300 mA (or 350 mV / Rsense) The theoretical power transfer is therefore: 1 2 @ Lp @ Ip2 @ Fsw + 2.2 W If this IC enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 2.2 . 0.1 = 220 mW. To better understand how this skip cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight: 1.4 V 4.8 V FB Normal Current Mode Operation Skip Cycle Operation Ipmin = 350 mV / Rsense Figure 17. Feedback Voltage Variations 3.8 V When FB is above the skip cycle threshold (1.4 V by default), the peak current cannot exceed 1 V/Rsense. When the IC enters the skip cycle mode, the peak current cannot go below Vpin1 / 4 (Figure 19). The user still has the flexibility to alter this 1.4 V by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. Figure 18. Output pulses at various power levels (X = 5 ms/div) P1<P2<P3 P1 P2 P3 Figure 19. The skip cycle takes place at low peak currents which guarantees noise free operation Max Peak Current Skip Cycle Current Limit |
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