SP8793

OPERATING NOTES

1. The clock input (Pin 5) should be capacitively coupled to

the signal source. The input signal path is completed by

coupling a capacitor from the internal bias decoupling, Pin 6 to

ground.

2. The output stage which is normally open collector (Pin 2

open circuit) can be interfaced to CMOS. The open collector

can be returned to a +10V line via a 5k resistor but the output

sink current should not exceed 2mA. If interfacing to TTL is

required then Pins 2 and 7 should be connected together to

give a fan-out = 1. This will increase supply current by

approximately 2mA.

3. The circuit will operate down to DC but a slew rate of better

than 20V/~s is required.

4. The mark space ratio of the output is approximately 1.2:1

at 200MHz.

5. Input impedance is a function of frequency. See Fig.5.

6. If no signal is present the device will self-oscillate. If this is

undesirable it may be prevented by connecting a 150k

between unused input and ground. This reduces the input

sensitivity by typically 50-100mV p-p.

7. The internal regulator has its input connected to Pin 8,

while the internal reference voltage appears at Pin 7 and

should be decoupled. For use from a 5.2V supply, Pins 7 and

8

should be connected together, and 5.2V applied to these

pins. For operation from supply voltages in the range +6.8V to

+9.5V, Pins 7 and 8 should be separately decoupled, and the

supply voltage applied to Pin 8.

Figure 5 : Typical impedance. Test conditions: supply voltage 5.2V, ambient temperature 25

°C, frequencies in

MHz, impedance normalised to 50 ohms.

Figure 6 : Toggle frequency test circuit

18

27

36

45

VCC1

CONTROL

INPUT

OUTPUT

VCC OF MODULUS

CONTROL DEVICE

1n

100n

1n

50

MONITOR

50

SIGNAL

SOURCE

VCC2

SEE OPERATING

NOTE 6