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CLC5957PCASM Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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CLC5957PCASM Datasheet(HTML) 9 Page - National Semiconductor (TI) |
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9 / 12 page  9 http://www.national.com Description The Evaluation board for the CLC5957 allows for easy test and evaluation of the product. The part may be ordered with all components loaded and tested. The order number is the CLC5957PCASM. The user supplies an analog input signal, encode signal and power to the board and is able to take latched 12-bit digital data out of the board. ENCODE Input (ENC) The ENCODE input is an SMA connector with a termination of 50 Ω. The encode signal is converted to an AC coupled, differential clock signal centered between VCC and ground. The user should supply a sinusoidal or square wave signal of >200mVpp and <4Vpp with a 50% duty cycle. The duty cycle can vary from 50% if the minimum clock pulse width times are observed. A low jitter source will be required for IF-sampled analog input signals to maintain best performance. CLC5957 Clock Option The CLC5957 evaluation board is configured for use with an optional crystal clock oscillator source. The compo- nent Y1 may be loaded with a ”Full-sized”, HCMOS type, crystal oscillator. Analog Input (AIN) The analog input is an SMA connector with a 50 Ω termination. The signal is converted from single to differential by a transformer with a 5 to 260MHz band- width and approximately one dB loss. Full scale is approx- imately 11dBm or 2.2Vpp. It is recommended that the source for the analog input signal be low jitter, low noise and low distortion to allow for proper test and evaluation of the CLC5957. Supply Voltages (J1 pins 31 A&B and 32 A&B) The CLC5957PCASM is powered from a single 5V supply connected from the referenced pins on the Euro- card connector. The recommended supplies are low noise linear supplies. Digital Outputs (J1 pins 7B (MSB, D11) through 18B (LSB) and 20B (Data Valid)) The digital outputs are provided on the Eurocard connector. The outputs are buffered by 5V CMOS latches with 50 Ω series output resistors. The rising edge of Data Valid may be used to clock the output data into data collection cards or logic analyzers. The board has a location for the HP 01650-63203 termination adapter for HP 16500 logic analyzers to simplify connection to the analyzer. CLC5957 Evaluation Board |
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