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IS61LV256-15J Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS61LV256-15J Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 8 page ISSI® IS61LV256 Integrated Silicon Solution, Inc. 2-1 Rev. F 0296 SR81995LV61 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc. FEATURES • High-speed access time: 12, 15, 20, 25 ns • Automatic power-down when chip is deselected • CMOS low power operation — 345 mW (max.) operating — 7 mW (max.) CMOS standby • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three-state outputs DESCRIPTION The ISSI IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable pro- cess coupled with innovative circuit design techniques, yields access times as fast as 12 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable ( CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil DIP and SOJ, plus the 450-mil TSOP package. IS61LV256 32K x 8 LOW VOLTAGE CMOS STATIC RAM FEBRUARY 1996 ISSI® FUNCTIONAL BLOCK DIAGRAM A0-A14 CE OE WE 256 X 1024 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 |
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