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ADS1256 Datasheet(PDF) 11 Page - Burr-Brown (TI) |
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ADS1256 Datasheet(HTML) 11 Page - Burr-Brown (TI) |
11 / 39 page ADS1255 ADS1256 SBAS288D − JUNE 2003 − REVISED AUGUST 2004 www.ti.com 11 OVERVIEW The ADS1255 and ADS1256 are very low-noise A/D converters. The ADS1255 supports one differential or two single-ended inputs and has two general-purpose digital I/Os. The ADS1256 supports four differential or eight single-ended inputs and has four general-purpose digital I/Os. Otherwise, the two units are identical and are referred to together in this data sheet as the ADS1255/6. Figure 5 shows a block diagram of the ADS1256. The input multiplexer selects which input pins are connected to the A/D converter. Selectable current sources within the input multiplexer can check for open- or short-circuit conditions on the external sensor. A selectable onboard input buffer greatly reduces the input circuitry loading by providing up to 80M Ω of impedance. A low-noise PGA provides a gain of 1, 2, 4, 8, 16, 32, or 64. The ADS1255/6 converter is comprised of a 4th-order, delta-sigma modulator followed by a programmable digital filter. The modulator measures the amplified differential input signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP − VREFN). The differential reference is scaled internally by a factor of two so that the full-scale input range is ±2VREF (for PGA = 1). The digital filter receives the modulator signal and provides a low-noise digital output. The data rate of the filter is programmable from 2.5SPS to 30kSPS and allows tradeoffs between resolution and speed. Communication is done over an SPI-compatible serial interface with a set of simple commands providing control of the ADS1255/6. Onboard registers store the various settings for the input multiplexer, sensor detect current sources, input buffer enable, PGA setting, data rate, etc. Either an external crystal or clock oscillator can be used to provide the clock source. General-purpose digital I/Os provide static read/write control of up to four pins. One of the pins can also be used to supply a programmable clock output. XTAL2 SPI Serial Interface Input Multiplexer and Sensor Detect Programmable Digital Filter A/D Converter 4th−Order Modulator VREFP VREFN Buffer V REF 2V REF AIN0 AIN1 AIN P AIN N AIN7 XTAL1/CLKIN RESET DRDY SCLK DIN SYNC/PDWN AIN2 AIN3 AIN4 AIN5 AIN6 AINCOM CS DOUT Control Clock Generator PGA 1:64 V IN • PGA Σ 2 Σ ADS1256 Only D3 D2 D1 D0/CLKOUT General Purpose Digital I/O Figure 5. Block Diagram |
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