Electronic Components Datasheet Search |
|
COP87L88RK Datasheet(PDF) 6 Page - National Semiconductor (TI) |
|
|
COP87L88RK Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 41 page AC Electrical Characteristics −40˚C ≤ T A ≤ +85˚C unless otherwise specified Parameter Conditions Min Typ Max Units Instruction Cycle Time (t c) Crystal, Resonator, 4.5V ≤ V CC ≤ 5.5V 1.0 DC µs R/C Oscillator 4.5V ≤ V CC ≤ 5.5V 3.0 DC µs Inputs t SETUP 4.5V ≤ V CC ≤ 5.5V 200 ns t HOLD 4.5V ≤ V CC ≤ 5.5V 60 ns Output Propagation Delay (Note 7) R L = 2.2k, CL = 100 pF t PD1,tPD0 SO, SK 4.5V ≤ V CC ≤ 5.5V 0.7 µs All Others 4.50V ≤ V CC ≤ 5.5V 1.0 µs MICROWIRE Setup Time (t UWS) (Note 7) V CC ≥ 4.5V 20 ns MICROWIRE Hold Time (t UWH) (Note 7) V CC ≥ 4.5V 56 ns MICROWIRE Output Propagation Delay (t UPD)VCC ≥ 4.5V 220 ns Input Pulse Width (Note 8) Interrupt Input High Time 1.0 t c Interrupt Input Low Time 1.0 t c Timer 1, 2, 3 Input High Time 1.0 t c Timer 1, 2, 3 Input Low Time 1.0 t c Reset Pulse Width 1.0 µs Note 2: tc = Instruction Cycle Time Note 3: Maximum rate of voltage change must be < 0.5 V/ms. Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load. Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal clock mode. Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex- cludes ESD transients. Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 8: Parameter characterized but not tested. www.national.com 6 |
Similar Part No. - COP87L88RK |
|
Similar Description - COP87L88RK |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |