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COP87L88RW Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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COP87L88RW Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 42 page  Reset This device enters a reset state immediately upon detecting a logic low on the RESET pin The RESET pin must be held low for a minimum of one instruction cycle to guarantee a valid reset During power-up initialization the user must in- sure that the RESET pin is held low until this device is within the specified VCC voltage An RC circuit on the RESET pin with a delay 5 times (5x) greater than the power supply rise time is recommended When the RESET input goes low the IO ports are initial- ized immediately with any observed delay being only propa- gation delay When the RESET pin goes high this device comes out of the reset state synchronously This device will be running within two instruction cycles of the RESET pin going high RESET may also be used to exit this device from the HALT mode Some registers are reset to a known state whereas other registers and RAM are ‘‘unchanged’’ by reset When the controller goes into reset state while it is performing a write operation to one of these registers or RAM that are ‘‘un- changed’’ by reset the register or RAM value will become unknown (ie not unchanged) This is because the write op- eration is terminated prematurely by reset and the results become uncertain These registers and RAM locations are unchanged by reset only if they are not written to when the controller resets The following initializations occur with RESET Port L TRI-STATE Port C TRI-STATE Port G TRI-STATE Port E TRI-STATE Port F TRI-STATE Port D HIGH PC CLEARED PSW CNTRL and ICNTRL registers CLEARED SIOR UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on T1CNTRL CLEARED T2CNTRL CLEARED TxRA TxRB RANDOM CCMR1 CCMR2 CLEARED CM1PSC CM1CRL CM1CRH CM2PSC CM2CRL and CM2CRH UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on CCR1 and CCR2 CLEARED CxPRH CxPRL CxCTH and CxCTL RANDOM after RESET at power-on PSR ENUR and ENUI CLEARED ENU CLEARED except Bit 1 (TBMT) e 1 Accumulator Timer 1 and Timer 2 RANDOM after RESET with crystal clock option (power al- ready applied) UNAFFECTED after RESET with RC clock option (power already applied) RANDOM after RESET at power-on MDCR CLEARED MDR1 MDR2 MDR3 MDR4 MDR5 RANDOM WKEN WKEDG CLEARED WKPND RANDOM S Register CLEARED SP (Stack Pointer) Loaded with 6F Hex B and X Pointers UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on RAM UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on The external RC network shown in Figure 6 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes TLDD12855 – 6 RC l 5 c POWER SUPPLY RISE TIME FIGURE 6 Recommended Reset Circuit Oscillator Circuits The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz The CKO output clock is on pin G7 (crystal configuration) The CKI input fre- quency is divided down by 10 to produce the instruction cycle clock (tc) Figure 7 shows the Crystal diagram TLDD12855 – 7 FIGURE 7 Crystal Diagram CRYSTAL OSCILLATOR CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator http www nationalcom 8 |
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Similar Description - COP87L88RW |
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