Electronic Components Datasheet Search |
|
M37736MHBXXXGP Datasheet(PDF) 9 Page - Mitsubishi Electric Semiconductor |
|
M37736MHBXXXGP Datasheet(HTML) 9 Page - Mitsubishi Electric Semiconductor |
9 / 96 page 9 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736MHBXXXGP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 7. Overflow flag (V) The overflow flag is effective only when addition or subtraction is performed with treating a word as a signed binary number. When the data length flag (m) is “0”, the overflow flag is set if the result of addition or subtraction is outside the range between – 32768 and +32767. When the data length flag (m) is “1”, the overflow flag is set if the result of addition or subtraction is outside the range between –128 and +127. It is reset in the other cases. The overflow flag can also be set or reset directly with the SEP or CLV, CLP instructions. 8. Negative flag (N) The negative flag is set when the result of arithmetic operation or data transfer is negative (If data length flag (m) is “0”, data bit 15 is “1”. If data length flag (m) is “1”, data bit 7 is “1”.) It is reset in the other cases. It can also be set or reset with the SEP or CLP instructions. 9. Processor interrupt priority level (IPL) The processor interrupt priority level (IPL) consists of 3 bits and determines the processor interrupt priority level (0 to 7). Interrupt is enabled when the interrupt priority level of the device requesting interrupt (the priority can be set using the interrupt control register) is higher than the processor interrupt priority level. When interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on interrupts for more details. BUS INTERFACE UNIT The CPU operates on an internal clock ’s frequency. Internal clock ’s frequency is twice the bus cycle frequency. In order to speed up processing, a bus interface unit is used to pre-fetch instructions when the data bus is idle. The bus interface unit synchronizes the CPU and the bus and pre-fetches instructions. Figure 4 shows the relationship between the CPU and the bus interface unit. The bus interface unit has a program address register, a 3-byte instruction queue buffer, a data address register, and a 2-byte data buffer. The bus interface unit obtains an instruction code from the memory and stores it in the instruction queue buffer, obtains data from the memory and stores it in the data buffer, or writes the data from the data buffer to the memory. Fig. 4 Relationship between the CPU and the bus interface unit CPU Bus interface unit E ALE BYTE HOLD BHE R/W D15 – D8 A23 – A0 D7 – D0 D'15 – D'8 Control signal D'7 – D'0 A'23 – A'0 |
Similar Part No. - M37736MHBXXXGP |
|
Similar Description - M37736MHBXXXGP |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |